Il 29/09/2014 14:07, Laszlo Ersek ha scritto: > Apparently so, for 00:01.3 on the PIIX4. > > But for other PCI devices, I think it's writeable, isn't it? (Of course > the devices-related code in this function should go away completely, if > possible. git-blame is probably helpful here.)
No, it's read-only. The PCI spec says so, and pci_init_wmask in QEMU's hw/pci/pci.c agrees (in QEMU, PCI_INTERRUPT_LINE is 0x3c, and PCI_INTERRUPT_PIN is 0x3d). >> > In fact, 0x3d should be _used_ to determine whether to fill in the >> > register at 0x3c, and what value to write. OVMF must write there the >> > GSI number associated to the corresponding INTX pin. See >> > pci_bios_init_device in SeaBIOS's src/fw/pciinit.c. > The PIIX4 spec says in 7.1.8. "INTLN—INTERRUPT LINE REGISTER (FUNCTION > 3)" that "The value in this register has no affect on PIIX4 hardware > operations." > > (It might still be useful for code that reads the register later, for > all I know.) Exactly. The OS will usually use 0x3d together with the result of _PRT to find the interrupt that is associated to a device; but the OS can also rely on the firmware's setting of 0x3c, which is basically the same thing but precomputed for non-ACPI-aware systems. >> > This should be done >> > in a PEI (or is it PI?) driver, not DXE, because it must run on resume >> > from S3. > The place would be MiscInitialization() in > "OvmfPkg/PlatformPei/Platform.c", but I'm not sure it would have any > effect. (Its lack doesn't seem to.) Likely not, but still it's wrong and the current code doesn't make much sense for Q35, so Gabriel may want to fix it anyway based on the Q35 DSDT. Paolo ------------------------------------------------------------------------------ Slashdot TV. Videos for Nerds. Stuff that Matters. http://pubads.g.doubleclick.net/gampad/clk?id=160591471&iu=/4140/ostg.clktrk _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel
