Hardcoded way to accomplish the equivalent of SeaBIOS's
pci_bios_init_devices(). Basically we initialize PCI_INTERRUPT_LINE
for every PCI device in the default q35 configuration based on
the final computed value SeaBIOS would have used.
This gets UHCI to work properly in OS X, so it's obviously the
Right Thing to do; I'm just not aware of how I'd actually enumerate
the PCI bus (or hook into gBS->ConnectController(), where the pci
bus gets enumerated currently) to add logic to initialize PCI_INTERRUPT_LINE
the right way.
For the record, the call tree is:
PlatformBdsPolicyBehavior()
...
ConnectRootBridge()
...
gBS->ConnectController() <--- PCI bus is scanned here
...
...
PlatformBdsConnectSequence()
...
PciInitialization() <---- this is where we currently set up LNK routing
and where the old stale piix code fiddling
with PCI_INTERRUPT_LINE and PCI_INTERRUPT_PIN
registers was removed from
...
...
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <[email protected]>
---
OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
index 3555d8a..72949c9 100644
--- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -751,6 +751,21 @@ PciAcpiInitialization (
PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x69), 0x0a); // LNKF
PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6a), 0x0b); // LNKG
PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), 0x0b); // LNKH
+ //
+ // In lieu of (re)scanning the PCI bus or a list of PCI devices
+ // built while scanning the PCI bus, similarly to the SeaBIOS
+ // behavior in pci_bios_init_devices(), which calculates what
+ // to write to 0x3c (PCI_INTERRUPT_LINE) based on what is read
+ // from 0x3d (PCI_INTERRUPT_PIN) using pci_slot_get_irq(), on
+ // a list constructed by pci_probe_devices().
+ //
+ PciWrite8 (PCI_LIB_ADDRESS (0, 2, 0, 0x3c), 0x0b);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 0, 0x3c), 0x0a);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 1, 0x3c), 0x0a);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 2, 0x3c), 0x0b);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 7, 0x3c), 0x0b);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 2, 0x3c), 0x0a);
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 3, 0x3c), 0x0a);
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
--
1.9.3
------------------------------------------------------------------------------
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