Merge PciInitialization() and AcpiInitialization() into a single function, PciAcpiInitialization(), and use a PCD set from PEI to use and initialize registers consistent with the underlying platform type (PIIX4 or Q35/MCH).
Add LNK[A-H] routing target initialization for the Q35 platform. For the PIIX4 platform, remove all PCI initialization calls other than setting up the LNK[A-D] routing targets; Some of the code being removed writes to 0x3d (PCI_INTERRUPT_PIN, which is RO), and the presence or absence of the remaining lines appears not to matter to the guest OS. I can only assume the code being removed is what remains from an early attempt to accomplish what SeaBIOS does with pci_bios_init_devices(), which calculates the (informational only, "no hardware action taken") value to be written to 0x3c (PCI_INTERRUPT_LINE) for the benefit of the guest OS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gabriel Somlo <[email protected]> --- OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c | 87 ++++++++++------------- OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h | 2 + OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf | 1 + 3 files changed, 40 insertions(+), 50 deletions(-) diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c index 2a1ca88..3555d8a 100644 --- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c @@ -717,63 +717,51 @@ Returns: VOID -PciInitialization ( +PciAcpiInitialization ( ) { - // - // Bus 0, Device 0, Function 0 - Host to PCI Bridge - // - PciWrite8 (PCI_LIB_ADDRESS (0, 0, 0, 0x3c), 0x00); - - // - // Bus 0, Device 1, Function 0 - PCI to ISA Bridge - // - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x3c), 0x00); - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x60), 0x0b); // LNKA routing target - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x61), 0x0b); // LNKB routing target - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x62), 0x0a); // LNKC routing target - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // LNKD routing target - - // - // Bus 0, Device 1, Function 1 - IDE Controller - // - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 1, 0x3c), 0x00); - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 1, 0x0d), 0x40); - - // - // Bus 0, Device 1, Function 3 - Power Managment Controller - // - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 3, 0x3c), 0x09); - PciWrite8 (PCI_LIB_ADDRESS (0, 1, 3, 0x3d), 0x01); // INTA - - // - // Bus 0, Device 2, Function 0 - Video Controller - // - PciWrite8 (PCI_LIB_ADDRESS (0, 2, 0, 0x3c), 0x00); - - // - // Bus 0, Device 3, Function 0 - Network Controller - // - PciWrite8 (PCI_LIB_ADDRESS (0, 3, 0, 0x3c), 0x0a); - PciWrite8 (PCI_LIB_ADDRESS (0, 3, 0, 0x3d), 0x01); // INTA (-> LNKC) + UINT16 HostBridgeDevId; + UINTN PMBA; // - // Bus 0, Device 5, Function 0 - RAM Memory + // Query Host Bridge DID to determine platform type // - PciWrite8 (PCI_LIB_ADDRESS (0, 5, 0, 0x3c), 0x0b); - PciWrite8 (PCI_LIB_ADDRESS (0, 5, 0, 0x3d), 0x01); // INTA (-> LNKA) -} - + HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId); + switch (HostBridgeDevId) { + case INTEL_82441_DEVICE_ID: + PMBA = POWER_MGMT_REGISTER_PIIX4 (0x40); + // + // 00:01.0 ISA Bridge (PIIX4) routing targets + // + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x60), 0x0b); // LNKA + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x61), 0x0b); // LNKB + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x62), 0x0a); // LNKC + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // LNKD + break; + case INTEL_Q35_MCH_DEVICE_ID: + PMBA = POWER_MGMT_REGISTER_Q35 (0x40); + // + // 00:1f.0 LPC Bridge (Q35) routing targets + // + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x60), 0x0a); // LNKA + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x61), 0x0a); // LNKB + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x62), 0x0b); // LNKC + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x63), 0x0b); // LNKD + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x68), 0x0a); // LNKE + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x69), 0x0a); // LNKF + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6a), 0x0b); // LNKG + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), 0x0b); // LNKH + break; + default: + DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", + __FUNCTION__, HostBridgeDevId)); + ASSERT (FALSE); + } -VOID -AcpiInitialization ( - VOID - ) -{ // // Set ACPI SCI_EN bit in PMCNTRL // - IoOr16 ((PciRead32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40)) & ~BIT0) + 4, BIT0); + IoOr16 ((PciRead32 (PMBA) & ~BIT0) + 4, BIT0); } @@ -938,8 +926,7 @@ Returns: // BdsLibConnectAll (); - PciInitialization (); - AcpiInitialization (); + PciAcpiInitialization (); // // Clear the logo after all devices are connected. diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h index 72b0e14..7006fb3 100644 --- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h +++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h @@ -59,6 +59,8 @@ Abstract: #include <Guid/HobList.h> #include <Guid/GlobalVariable.h> +#include <OvmfPlatforms.h> + extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[]; extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[]; diff --git a/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf b/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf index a2b72ba..03f5b22 100644 --- a/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf +++ b/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf @@ -58,6 +58,7 @@ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId [Pcd.IA32, Pcd.X64] gEfiMdePkgTokenSpaceGuid.PcdFSBClock -- 1.9.3 ------------------------------------------------------------------------------ _______________________________________________ edk2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/edk2-devel
