PCI bus contains three type of memory: - PCI Configuration Space
- PCI I/O Space - PCI Memory Space RootBridgeIoMemWrite () writes to 'PCI Memory Space'. I would say the description matches your interpretation if you assume 'PCI controller' is the same as what you named '(PCI) devices'. Your (PCI) device is attached to a PCI root bridge (what you names as 'PCI 3.0 controller'). You can potentially have more than one PCI controller on your platform. RootBridgeIoIoRead () reads to 'PCI I/O Space'. BAR means 'Base Address Register'. They are actually read from the PCI configuration space but they point to the different PCI I/O & Mem spaces. You have different types of BAR. BAR for I/O Space, BAR for PCI 32bit Memory, BAR for PCI 64bit prefetechable Memory, etc From: Leekha Shaveta [mailto:shav...@freescale.com] Sent: 16 June 2015 11:50 To: edk2-devel@lists.sourceforge.net Cc: Deepak Chauhan; Konda Ravi Subject: [edk2] some queries in "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" implementation Hi, I was implementing "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" protocol for PCI 3.0 controlller, I have few more basic queries like: (1) In function: EFI_STATUS EFIAPI RootBridgeIoMemWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer ); The description says: "Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller registers in the PCI root bridge memory space." What does this mean? I thought that Mem.Read/Mem.Write means reading memory space that is kept/allocated to various memory devices. But this description seems to say different. (2) Similarly "Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space." For function: EFI_STATUS EFIAPI RootBridgeIoIoRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT64 UserAddress, IN UINTN Count, OUT VOID *UserBuffer ); What is this PCI root bridge I/O and Memory space? As I have seen that these Mem.Read/mem.Write and Io.Read/Io.Write functions have been used by PCI Bus driver for reading "BarIndex" at various stages. Aren't all BAR registers in PCI configuration space? Kindly help in clearing these doubts. Thanks and Regards, Shaveta -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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