From: Leekha Shaveta [mailto:shav...@freescale.com] Sent: 16 June 2015 12:59 To: edk2-devel@lists.sourceforge.net; Olivier Martin Cc: Deepak Chauhan; Konda Ravi Subject: RE: [edk2] some queries in "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" implementation
Thanks Olivier! Please find my doubts and replies in-lined. Thanks and Regards, Shaveta From: Olivier Martin [mailto:olivier.mar...@arm.com] Sent: Tuesday, June 16, 2015 4:53 PM To: edk2-devel@lists.sourceforge.net<mailto:edk2-devel@lists.sourceforge.net> Cc: Chauhan Deepak-B10991; Theja Ravi-B11286 Subject: Re: [edk2] some queries in "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" implementation PCI bus contains three type of memory: - PCI Configuration Space - PCI I/O Space - PCI Memory Space RootBridgeIoMemWrite () writes to 'PCI Memory Space'. I would say the description matches your interpretation if you assume 'PCI controller' is the same as what you named '(PCI) devices'. [Shaveta]: True! As config space is also mapped to memory in PCI 3.0 ? and we can get same registers in memory also? [Olivier] PCI Config Space is also present in your CPU Memory Map when using PCI 3.0. Your (PCI) device is attached to a PCI root bridge (what you names as 'PCI 3.0 controller'). You can potentially have more than one PCI controller on your platform. RootBridgeIoIoRead () reads to 'PCI I/O Space'. [Shaveta] What is this PCI IO space? And how PCI controller's registers can be read from PCI IO space? [Olivier] PCI I/O space: https://en.wikipedia.org/wiki/Conventional_PCI#PCI_address_spaces PCI I/O space is not supported on ARM architectures. BAR means 'Base Address Register'. They are actually read from the PCI configuration space but they point to the different PCI I/O & Mem spaces. [Shaveta] Yes in PCI 3.0, all BARs are in PCI config space. But in PCI bus implementation in MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c For example In function: EFI_STATUS EFIAPI PciIoPollIo ( IN EFI_PCI_IO_PROTOCOL *This, IN EFI_PCI_IO_PROTOCOL_WIDTH Width, IN UINT8 BarIndex, IN UINT64 Offset, IN UINT64 Mask, IN UINT64 Value, IN UINT64 Delay, OUT UINT64 *Result ) Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result); Why PciIoIoRead is used to read the BAR ? Or is it actually reading the IO space specified in this given BAR? [Olivier] BAR represents PCI I/O or Memory space. PciIoRead() does not read the BAR but PciIoRead() uses the BAR. You have different types of BAR. BAR for I/O Space, BAR for PCI 32bit Memory, BAR for PCI 64bit prefetechable Memory, etc From: Leekha Shaveta [mailto:shav...@freescale.com] Sent: 16 June 2015 11:50 To: edk2-devel@lists.sourceforge.net<mailto:edk2-devel@lists.sourceforge.net> Cc: Deepak Chauhan; Konda Ravi Subject: [edk2] some queries in "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" implementation Hi, I was implementing "EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL" protocol for PCI 3.0 controlller, I have few more basic queries like: (1) In function: EFI_STATUS EFIAPI RootBridgeIoMemWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer ); The description says: "Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller registers in the PCI root bridge memory space." What does this mean? I thought that Mem.Read/Mem.Write means reading memory space that is kept/allocated to various memory devices. But this description seems to say different. (2) Similarly "Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space." For function: EFI_STATUS EFIAPI RootBridgeIoIoRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT64 UserAddress, IN UINTN Count, OUT VOID *UserBuffer ); What is this PCI root bridge I/O and Memory space? As I have seen that these Mem.Read/mem.Write and Io.Read/Io.Write functions have been used by PCI Bus driver for reading "BarIndex" at various stages. Aren't all BAR registers in PCI configuration space? Kindly help in clearing these doubts. Thanks and Regards, Shaveta -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. 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