> Guess we will have to await independent testing. The Flex folks seem
> to assert they have the equivalent of more than 24 bit when dealing
> with adjacent strong signals.

Yes we will need to wait for independent testing but given relatively
wide filters (200 KHz or more), that testing can't be done with only
two signals.  The tests will need to be (notched) noise power tests or
multiple tone tests that stress the *total* power handling capability
of the system.

It is the huge increase in instantaneous peak voltage when multiple
signals are present that causes multi-channel (multiplexed) power
amplifiers to be rated for peak powers as much as 20 dB higher that
their average operating (output) power.  The same problem of peak to
average power (voltage) *will* impact the absolute voltage handling
requirements of the ADC used in any DDC system.  Decimation may
improve resolution but not the absolute maximum and minimum signal
levels.

73,

    ... Joe, W4TV


On 5/19/2012 8:23 PM, Tom Azlin N4ZPT wrote:
> Hi Joe,
>
> Guess we will have to await independent testing.  The Flex folks seem to
> assert they have the equivalent of more than 24 bit when dealing with
> adjacent strong signals.
>
>   From the Flex reflector...
>
>> Just in rough numbers, you get a 1/2-bit for every divide-by-two decimation
>> you do.  If you are looking at dynamic range in a 500Hz bandwidth (this is
>> what we typically do).  The math I generally use to get there is
>> log(f1/f2)/log(2)/2.  I just think this way as a programmer (do everything
>> in base 2). So if you take log(245.76E6/500)/log(2)/2 you get 9.4 extra
>> bits when added to the 16 gives you 25.5 bits (152.7dB dynamic range).
>>   This assumes all 16-bits of the ADC are "good" which is probably not a
>> good assumption.  I'd have to pull out the notes and look at the data sheet
>> again, but this should give you a rough idea.  Hopefully I haven't made an
>> additional "duh" today myself!
>>
>> Bottom line -- there's plenty of dynamic range.
>>
>> Also, if you are interested, we are using Xilinx DSP48E1 blocks which use
>> an 18x25 multiplier and so Xilinx tools generate the on-board DDS as a
>> 25-bit DDS by default --- again to preserve the SFDR of the receiver.  We
>> could add extra bits, but 25 are fine for the same reason.
>>
>> Steve
>>
>> Stephen Hicks, N5AC, AAR6AM
>> VP Engineering
>> FlexRadio Systems™
>> 4616 W Howard Ln Ste 1-150
>> Austin, TX 78728
>> Phone: 512-535-4713 x205
>> Email: steve at flexradio.com
>> Web: www.flexradio.com
>
>
> On 5/19/2012 8:11 PM, Joe Subich, W4TV wrote:
>>
>> Decimation can help but it is not a magic bullet that eliminates
>> the effects of ADC overflow and/or blocking due to gain reduction.
>>
>> 73,
>>
>> ... Joe, W4TV
>>
>>
>> On 5/19/2012 7:57 PM, Tom Azlin N4ZPT wrote:
>>> decimation counts
>>>
>>> On 5/19/2012 7:29 PM, Joe Subich, W4TV wrote:
>>>> The issue will be the severely limited dynamic range of the 16 bit
>>>> ADC. Without effective AGC ahead of the ADC there *will* be overload
>>>> problems on crowded bands (e.g. 160/80/40) where any transceiver must
>>>> deal with many extremely strong ("local") signals while maintaining
>>>> maximum sensitivity. With AGC, the strong local signals will cause
>>>> "blocking" as the gain is reduced to prevent overflow of the ADC.
>>>
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>>
>
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