For some reason I can't open that attachment. Did you get mine?
Jan Bissey Micron Technology 208.368.3066 WWSD __o _ \<_ ......(_)/(_) -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Lincoln Bollschweiler Sent: Thursday, October 08, 2009 1:12 PM To: [email protected] Subject: RE: getting a global plane into a hierarchical cell Hi Jan, I added a pure layer of Metal 1 over the top of your VDD. I connected that pure layer to one of your VDDs (might want to connect to all of them??). I exported that pure layer. I then made a new cell called NextLevel and connected M1 to it. Take a look. Is that what you were after? Regards, Lincoln -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Jan Sent: Thursday, October 08, 2009 12:58 PM To: Electric VLSI Editor Subject: getting a global plane into a hierarchical cell I have an inverter cell created in layout. Node names are vdd, gnd, in, out. I want to now create a string of inverters so I create a new cell, called test_lay, and place some of the inverters in there and connect them up. How do I get the vdd and gnd nodes to be one solid node in this second layout? I have attached a jelib for you to take a look. For example I can't get the entire bottom node to be gnd. Why do I want this? Because the next level up in the hierarchy, test2_lay, I want to have this string of inverters to be connected on the left and right to the adjacent cells vdd and gnd busses. The way I see around this is to create another bus in each hierarchy that becomes the common bus, gnd or vdd, for that level. Seems redundant and unnecessary. I ahve posted a jelib called test.jelib Ideas? --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en -~----------~----~----~----~------~----~------~--~---
test.jelib
Description: test.jelib
