Jan, does the attached help? Jake. On Thu, Oct 8, 2009 at 12:57 PM, Jan <[email protected]> wrote:
> > I have an inverter cell created in layout. Node names are vdd, gnd, > in, out. I want to now create a string of inverters so I create a new > cell, called test_lay, and place some of the inverters in there and > connect them up. How do I get the vdd and gnd nodes to be one solid > node in this second layout? I have attached a jelib for you to take a > look. For example I can’t get the entire bottom node to be gnd. > Why do I want this? Because the next level up in the hierarchy, > test2_lay, I want to have this string of inverters to be connected on > the left and right to the adjacent cells vdd and gnd busses. > The way I see around this is to create another bus in each hierarchy > that becomes the common bus, gnd or vdd, for that level. Seems > redundant and unnecessary. > I ahve posted a jelib called test.jelib > Ideas? > > > -- http://CMOSedu.com/jbaker/jbaker.htm --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en -~----------~----~----~----~------~----~------~--~---
test_jb.jelib
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