Hi Rob, I believe it's layer to substrate. There isn't, as far as I know, a layer to layer parasitic extraction since that could/would require special care to ensure that the resulting SPICE netlist was practical to simulate. I believe this is why separate tools are used (e.g. StarRC) for parasitic extractions in most design flows.
This augmented extraction (layer-to-layer) would be a nice addition to Electric especially if we could download a jelib with the parasitics (and design/electrical rules) set for a particular process. Good luck, Jake. On Thu, Dec 3, 2009 at 7:15 AM, Rob <[email protected]> wrote: > I need some clarification on changing the parasitic values for a given > technology. I am using MOSIS test data as a reference for parasitic > values for latest TSMC 0.18um processes run. > I can only assume that the resistance property is given in ohm/square. > If I am wrong please let me know. Where I am confused is which > parasitic capacitance parameter to put in the "Area Cap" and > "Perimeter Cap" properties. Do I assume that for each layer it is > “layer to substrate” or “layer (n) to layer (n-1)” capacitance? My > best guess is layer to substrate capacitance for both. Could somebody > please clarify this for me. > > Thank you in advance > Rob > > -- > > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > > > -- http://CMOSedu.com/jbaker/jbaker.htm -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
