Hi, I am trying to use the poly1-poly2 capacitor in my designs, but have not been able to NCC the designs. The NCC error arises due to the fact that Electric considers the pol1-poly2 plates in the layout as a short and merges the net name.
In the attached jelib, the cell "Cap_test_DRC" has a capacitor laid out such that the nets p1 and p2 are separate and NCC fine. However this cell fails DRC check due to the unconnected poly overlap. On the other hand, in the cell "Cap_test_NCC", the poly1' s are connected and pass the DRC check. However, the nodes p1 and p2 are merged by Electric. This merging of net is causing NCC errors in larger designs where such capacitor is used. For an example of the problem, see the switched-capacitor cell "Switched_Cap". This cell DRC's fine, but has issues with NCC due to the merging of the top and bottom plate nets in the layout. Any suggestions on this issue are welcome. Thanks Vishal--
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Cap_Test.jelib
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