Regds Vishal Sent from my iPhone
On Jan 10, 2010, at 9:34 AM, Jake Baker <[email protected]> wrote:
--Hi Vishal, I got the Cap_test_DRC in the attached to NCC and DRC correctly.However, when I try to generate a SPICE netlist from the layout view of this cell I get an Exception Caught!!! See attached log file (for the developers).Also, the contact opening (poly cut) isn't corrrect in this p1-p2 Cap node, it should be an array of 2 by 2 cuts not one big opening (I tried to change the Node's properties to fix this but had no success).Finally, I couldn't get the Switched_Cap cell to NCC because of the shorting error you mentioned.Sooo, I made the cap_100f group in the attached (you'll have to adjust the size so the p1-p2 overlap is 100fF). I then modified the Switched_Cap cell to show it worked. See v2 of this cell in the attached.Hope this is useful, Jake.On Sat, Jan 9, 2010 at 10:09 PM, Vishal Saxena <[email protected]> wrote:Hi,I am trying to use the poly1-poly2 capacitor in my designs, but have not been able to NCC the designs. The NCC error arises due to the fact that Electric considers the pol1-poly2 plates in the layout as a short and merges the net name.In the attached jelib, the cell "Cap_test_DRC" has a capacitor laid out such that the nets p1 and p2 are separate and NCC fine. However this cell fails DRC check due to the unconnected poly overlap.On the other hand, in the cell "Cap_test_NCC", the poly1' s are connected and pass the DRC check. However, the nodes p1 and p2 are merged by Electric. This merging of net is causing NCC errors in larger designs where such capacitor is used.For an example of the problem, see the switched-capacitor cell "Switched_Cap". This cell DRC's fine, but has issues with NCC due to the merging of the top and bottom plate nets in the layout.Any suggestions on this issue are welcome. Thanks Vishal --You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group.To post to this group, send email to [email protected].To unsubscribe from this group, send email to [email protected] . For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en .-- http://CMOSedu.com/jbaker/jbaker.htm --You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group.To post to this group, send email to [email protected].To unsubscribe from this group, send email to [email protected] . For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en .<Cap_Test_jb.jelib> <electric.log>
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