At 11:38 AM 7/2/2011, you wrote:
Hi everybody,I'm trying to generate the layout of a full adder from a vhdl description. The full adder is made with two half adders and an or gate, as usual. I've already created the layout of the half adder and the or gate, now i need electric to create the layout of the full adder. When I select Silicon Compiler -> Convert current cell to layout, the compiler returns a java exception: Cannot create arc Metal-1 from (4.0,177.0) to (-20.0,177.0) in cell 'FULL_ADDER{lay}' because it cannot connect to port vdd on node HALF_ADDER{lay}[node1] java.lang.NullPointerException at com.sun.electric.database.topology.ArcInst.makeInstanceBase(ArcInst.java: 225) etc......... What can be the cause of this?
Can the Metal-1 arc connect to the VDD port on your half-adder node? Are they in the same technology?
I would need to see your JELIB file to know for sure. -Steven Rubin -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
