At 01:16 AM 2/1/2013, you wrote:
Greetings to all members.
I am trying to use the Silicon Compiler tool in order to convert a
schematic to layout, but i cant figure how it works. The electric
manual says very few about that issue.
With my scematic i choose tools -> Silicon Compliler -> Convert
current cell to layout.
After that electric produce a new library called "sclib", full of
some layouts gates.
Can you please give me any help about that ?
The compiler places and routes cells from a standard-cell library.
One such library comes with Electric, but it is old and you will
probably want your own. The manual describes the cells that the
library should have. The compiler places and routes a netlist that
makes reference to the cells in the library. If you have VHDL code,
it is compiled to the netlist first. And if you are converting a
schematic cell, then it actually generates VHDL for that schematic,
compiles the VHDL, and then places and routes the netlist.
So you can see what it's doing by looking at the VHDL cell that gets
created. It should refer to cells in your standard cell library.
-Steven Rubin
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