Hello, LTspice is not able to find the subcircuit.Usually, you have to place every module in the same folder. In case it still doesn’t solve the problem, kindly share your jelib file.
On Tue, Mar 12, 2013 at 11:48 AM, Saraslife <[email protected]> wrote: > I have designed a Carry Look Ahead Adder using NAND and NOR gates. The > schematic is perfect, simulation results are correct. > > Now, while simulating layout, LTSpice gave an error saying "unknown > subcircuit called in". > > I have individually simulated each sub-circuit used in the design, no > errors was encountered. Also, there is no problem with DRC & NCC. The > schematic matches with Layout in all respects. > > Kindly, post if you can diagnose the location of the problem or you > suffered the same problem. I really need to find the solution. > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/groups/opt_out. > > > -- Best Regards, Mohammad A Maktoomi M.TECH(Electronic circuits & systems design) ,2011-2013 Electronics Engineering Department Aligarh Muslim University INDIA-202002 www.maktoomi.blogspot.com Contact: +91-9540642271 ***************************** -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
