Hi! You can find here[1] in table 2c and 2b that for TSMC 180nm you have two options: SCN6M_SUBM with lambda 0.1 um SCN6M_DEEP with lambda 0.09 um
Saludos! Leandro. [1]: https://www.mosis.com/files/scmos/scmos.pdf 2015-02-19 22:16 GMT-03:00 Gunasekhar Aluru <[email protected]>: > Electric has only design rules from MOSIS right? > > In MOSIS design rules lambda is minimum of 0.09 for TSMC 180nm process. > > 1) So my question is can we design a layout with lamda=0.09 or 90nm for > TSMC 0.18nm process in electric tool ? > > 2) And the design rules of Actual TSMC for 180nm various with Design rules > of MOSIS TSMC 180nm process right? > > 3) So what is the minimum technology size that i can use to design layout > in electric without DRC errors satisfying Design rules.? Is it lamda=100nm > for TSMC 180nm process? > > 4) So can i say that we can do 180nm technology with MOSIS submicron > design rules with lamda=100nm and 90nm ?. > > Please Please answer this question. > > Thanks in advance. > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
