Electric has only design rules from MOSIS right?
No, Electric has design rules for more than just MOSIS.
You can have a look at:
http://www.staticfreesoft.com/jmanual/mchap07-04-02.html
The use of MOSIS with SCMOS design rules is probably most common.
However, as it describes in section 7-4-2 of the Electric manual, you
can also select the submicron or deep rules.
You can also see:
http://www.staticfreesoft.com/jmanual/mchap07-01-01.html
As you can see in the section 7-1-1 of the Electric manual, there are
other technologies, like cmos, with different design rules.
In MOSIS design rules lambda is minimum of 0.09 for TSMC 180nm process.
1) So my question is can we design a layout with lamda=0.09 or 90nm
for TSMC 0.18nm process in electric tool ?
I think layouts for the TSMC 180 nm process technology have been done
before with Electric. It is probably why when you click Help->About
Electric, then click Plugins that you should see "Missing: Technologies
(cmos90, tsmc180)". However, I suspect that the TSMC technology is
proprietary, such that the plugin cannot be found on the internet. I'm
not sure where to get the plugin, maybe from TSMC or Dr. Rubin (by
non-public email)?
2) And the design rules of Actual TSMC for 180nm various with Design
rules of MOSIS TSMC 180nm process right?
It looks like there are MOSIS TSMC design rules that are compatible with
actual TSMC as Leandro has already pointed out (Table 2b and 2c in
https://www.mosis.com/files/scmos/scmos.pdf).
However, it seems that there can be differences between them. You should
see at
https://www.mosis.com/pages/design/rules
that it says "Use vendor specific rules for fine-tuned layout." If you
are interested in different vendors, there is a list at:
https://www.mosis.com/products/fab-processes
3) So what is the minimum technology size that i can use to design
layout in electric without DRC errors satisfying Design rules.?
I don't think that there is a limit on the minimum technology size that
you can use as long as it is greater than zero and you have set the
appropriate design rules for your minimum technology.
You might also have a look at section "1.5.3 Layout Design Rules" on
page 24 in the Introduction chapter of CMOS VLSI Design (4th Edition) by
Neil H. E. Weste and David Money Harris [ Click Look Inside and the then
Introduction link at http://pages.hmc.edu/harris/cmosvlsi/4e/ ].
According to what it says, it looks like you should be able to change
just lambda without having to change the MOSIS (mocmos) design rules in
Electric for 180 nm process technology. However, for process
technologies below 180 nm, it indicates that the design rules would have
to be altered as they become complex and process specific.
Is it lamda=100nm for TSMC 180nm process?
I believe the TSMC 180 nm process is limited typically to a minimum
technology size of lambda = (180 nm process)/2 = 90 nm.
4) So can i say that we can do 180nm technology with MOSIS submicron
design rules with lamda=100nm and 90nm ?.
Based on Table 2b and 2c in scmos.pdf, I would say the answer is yes.
However, it seems better to describe the design rules at lambda = 90 nm
as "deep submicron" like in Table 2c as the term "submicron" appears to
be reserved for the processes in Table 2b.
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