Hello: I'm trying to export a layout designed in Electric to the GDSII format. By consulting the layer numbers in the Preferences, I saw that the "passivation layer" is the same as the "glass layer". For the SCMOS Technology, this layer code is 52. However, by analyzing the chip examples, this layer is used exactly where you don't want to be passivated, that is, the bonding openings. Is the passivation layer used in the areas where you do not want to have a glass passivation?
Any help is welcome. Thanks, Estevao -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
