On Sat, 12 Jun 2021 12:22:54 -0700 (PDT) "'shalan' via Electric VLSI Editor" <[email protected]> wrote: > Btw, I helped designing the harness chip (Caravel) being used for > this program.
Thank you for your work on this! I think Caravel is an awesome idea and an impressive accomplishment. The only thing that is not-awesome is the fact that it is mandatory to use it as a monolith. I hope that changes. Really all that should be required is that the UBM and top metal layer match Caravel in order to allow all the projects to be WLCSP-packaged in a single run. > Finally, have you seen this: > https://www.efabless.com/chipignite/2106Q? No, I had not seen that. It looked very promising, except: > How It Works > ... > 3. Complete your project using the Caravel carrier-chip design I would assume from this that using all of Caravel is still mandatory. However, you write: > with the option to use the full die area the way you want. ... so perhaps my interpretation of the rules was too pessimistic? > I recommend that you get in touch with mkk at efabless.com Thank you; I will send an email to that address for clarification and CC you. I've also replied to you directly with answers to your other questions. - a -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/20210612213444.7131ba77%40ostraka.
