Sebastian Kuzminsky wrote:
> So... If the human asks for (for example) 1 microsecond 
> StepLen+StepSpace, and the driver thinks the stepgen clock runs at 
> 33,000,000 ticks/second, then it's going to ask for 33 ticks.  But if 
> the stepgen clock in reality runs at 30 MHz, then those 33 ticks will 
> take 1.1 microseconds, and the max step rate will be 10% less than what 
> everyone thinks.  The human diligently computes the axis MAX_VELOCITY 
> based on the 33 MHz stepgen clock, then gets ferrors when the actual 
> setpgen clock is slower than that.

Replying to myself here...

When the driver asks the firmware for a step rate that is higher than 
the firmware's timing parameters allow it to deliver, the firmware 
"stalls" or "throttles" the step generator, pausing step output until 
timing requirements have been satisfied.

I'm wondering...  When this happens, does the Dir pin see the stall? 
Specifically, if i've commanded a very large negative step rate and the 
firmware throttles the output to comply with timing parameters, does the 
Dir pin see the internal velocity go to 0 (necessitating a DirSetup 
pause), then go back to 1 again when the timing constraint has been met 
(necessitating another pause)?

I dont know VHDL well enough to just look up the answer for myself in 
the source...


-- 
Sebastian Kuzminsky
the sky calls to us -- carl sagan
<http://www.youtube.com/watch?v=zSgiXGELjbc>

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