What about top and bottom of a board? What would happen (assuming 60950) if you had AC on the component side of a board and SELV on the solder side. (assuming that any through holes were properly cleared out).
How acceptable is that? Chris Maxwell | Design Engineer - Optical Division email chris.maxw...@nettest.com | dir +1 315 266 5128 | fax +1 315 797 8024 NetTest | 6 Rhoads Drive, Utica, NY 13502 | USA web www.nettest.com | tel +1 315 797 4449 | > -----Original Message----- > From: John Juhasz [SMTP:jjuh...@fiberoptions.com] > Sent: Friday, February 01, 2002 2:31 PM > To: 'j...@aol.com'; rbus...@es.com > Cc: emc-p...@majordomo.ieee.org > Subject: RE: Pollution Degree vs. Creapage Distance > > Just some anecdotal info . . . > There was an occassion at a previous employ where, due to a brief > mental > hiccup on the part of several folks, a printed circuit get fabricated > with not enough spacing > (damn close though to the required) between a mains trace and > secondary in an > internal layer for a card-cage backplane. > The discussion that ensued with knowledgable folks at a well-known > NRTL > brought forth the following: > a) Extra tests - thermal aging and thermal cycling tests need to be > performed. Time consuming and expensive. > b) Tight quality control on the part of the fabricator to > ensure layer dimensions, adhesion, etc. > Reduces flexbility to change vendors at a moment's > notice. > c) Routine electric strength testing by us. > > In short, they noted that while possible, it is difficult to maintain > the > pollution degree 1 in a printed circuit. Typically the pollution > degree > is applied to 'potted' items. > > Taking all into consideration it was easier for us (and less > expensive) > to respin the board. > > John Juhasz > Fiber Options > Bohemia, NY > > > > -----Original Message----- > From: j...@aol.com [mailto:j...@aol.com] > Sent: Friday, February 01, 2002 12:50 PM > To: rbus...@es.com > Cc: emc-p...@majordomo.ieee.org > Subject: Re: Pollution Degree vs. Creapage Distance > > > > In a message dated 1/31/2002, Rick Busche writes: > > > > > Does the application of a solder mask allow for a change > from pollution degree 2 to pollution degree 1? I understand that > conformal coating requires significant testing when used to reduce > spacings per table 7, but in this case I am only asking if solder mask > can be used to improve the pollution concern. > > > > > > Hi Rick: > > You do not mention which standard you are looking at, but if it > is one of the IEC 950 derivatives there are some clauses that > specifically address the questions you have. For example, in EN > 60950, Third Edition, clause 2.10.5.3 addresses printed circuit > boards, and clause 2.10.6 addresses solder mask. To the extent you > can use inner layers, clause 2.10.5.3 should provide you some of the > relief you seek. > > I have not ever tried to qualify a solder mask under clause > 2.10.6 due to the burden of the additional tests, but you may want to > consider it. > > > > Joe Randolph > Telecom Design Consultant > Randolph Telecom, Inc. > 781-721-2848 > http://www.randolph-telecom.com > ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Michael Garretson: pstc_ad...@garretson.org Dave Heald davehe...@mediaone.net For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: No longer online until our new server is brought online and the old messages are imported into the new server.
