Hi Rick,
I am assuming (ugh) that you are referring to EN60950 2nd Edition. If so,
clause 2.9.6 clearly
addresses your question by requiring hermetic sealing or such enclosing to
prevent the ingress of
dirt and/or moisture. IMHO, solder mask does not and cannot provide this type
of protection and,
therefore, cannot be used as such.
And, as for your question, "Why are the secondary circuit spacing requirements
based on a primary
input voltage?". Look into Annex ZB of the above standard and then to the
reference clause 6.2.1.2.
Your answer is there as it relates to TNV circuits.
Again, this is assuming that you were referring to the above standard.
I hope this helps.
Best regards,
Ron Pickard
rpick...@hypercom.com
rbus...@es.com
Sent by: To:
emc-p...@majordomo.ieee.org
owner-emc-pstc@majordom cc:
o.ieee.org Subject: Pollution
Degree vs. Creapage Distance
01/31/02 01:01 PM
Please respond to
rbusche
I am wading through the creapage and clearance requirements for secondary
circuits using the values
in tables 5 and 6. It becomes very apparent that the creapage distances become
quite large when you
assume material group IIIb (CTI). For operational insulation, this might be
2-3X the clearance
values. My question to the group is:
Does the application of a solder mask allow for a change from pollution degree
2 to pollution degree
1? I understand that conformal coating requires significant testing when used
to reduce spacings
per table 7, but in this case I am only asking if solder mask can be used to
improve the pollution
concern.
Assuming this is NOT the case, are there any other practical suggestions?
Cutting slots in
multilayer cards is a bit tricky. I can live with 0.7mm of clearance, but 2.5
mm (operational) or
5.0 (reinforced) of creapage is a bit difficult on a densely populated power
supply.
One last question. Why are the secondary circuit spacing requirements based on
a primary input
voltage?
Thanks
Rick Busche
E&S
rbus...@es.com
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