I am wading through the creapage and clearance requirements for secondary circuits using the values in tables 5 and 6. It becomes very apparent that the creapage distances become quite large when you assume material group IIIb (CTI). For operational insulation, this might be 2-3X the clearance values. My question to the group is:
Does the application of a solder mask allow for a change from pollution degree 2 to pollution degree 1? I understand that conformal coating requires significant testing when used to reduce spacings per table 7, but in this case I am only asking if solder mask can be used to improve the pollution concern. Assuming this is NOT the case, are there any other practical suggestions? Cutting slots in multilayer cards is a bit tricky. I can live with 0.7mm of clearance, but 2.5 mm (operational) or 5.0 (reinforced) of creapage is a bit difficult on a densely populated power supply. One last question. Why are the secondary circuit spacing requirements based on a primary input voltage? Thanks Rick Busche E&S rbus...@es.com ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Michael Garretson: pstc_ad...@garretson.org Dave Heald davehe...@mediaone.net For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: No longer online until our new server is brought online and the old messages are imported into the new server.
