All,

Clock frequency:  100MHz
Rise Time: 1.5ns
Voltage pk-pk: 3.3V
Traces are impedance controlled, and in a stripline configuration


Scott





|---------+--------------------------->
|         |           RPickard@hyperco|
|         |           m.com           |
|         |                           |
|         |           10/24/2002 02:26|
|         |           PM              |
|         |                           |
|---------+--------------------------->
  
>-------------------------------------------------------------------------------------------------------------------------------|
  |                                                                             
                                                  |
  |        To:      scott....@jci.com                                           
                                                  |
  |        cc:      emc-p...@majordomo.ieee.org                                 
                                                  |
  |        Subject: Re: High Speed Clock Routing                                
                                                  |
  
>-------------------------------------------------------------------------------------------------------------------------------|





Hi Scott,

First, I think we all need a bit more information for a specific response.
Such as:

- what is the clock frequency?
- what is the clock rise time?
- what is the clock signal amplitude?
- overshoot or undershoot?
- are these clock traces impedance controlled?
- stripline or microstrip?

And, you probably won't get a specific response anyway. That's what
consultants are for.  :-)

But for rules of thumb with clock traces (and other high energy traces), it
is important to keep
layer changes to a minimum, if not zero, and keep them routed away from
other susceptible traces to
reduce crosstalk. In general, use a series termination located next to the
output pin. Also, almost
always avoid trace branches for clock traces. Its also important to keep
everything well decoupled.

IHTH.

Best regards,

Ron Pickard
rpick...@hypercom.com





                      owner-emc-pstc@majordo

                      mo.ieee.org                   To:
emc-p...@ieee.org

                                                    cc:

                      10/24/02 10:20 AM             Subject:  High Speed
Clock Routing
                      Please respond to

                      Scott.Mee








All,

I have a question regarding trace routing for high-speed clock signals.

I have one driver, and two receivers.  The distance between the driver and
1st receiver is roughly 2.5cm, the distance between 1st receiver and 2nd
receiver is 3cm, and the distance between driver and 2nd receiver is 3.5cm.

I actually have 2 questions:

      1) What is a good rule of thumb for routing and termination of this
high-speed clock trace?
      2) Is daisy chain routing preferred (meaning driver to 1st receiver,
then 2nd receiver), or should 2 traces of equal length be routed, 1 to each
receiver (each of these two traces will have twice the impedance of the
single trace emanating from the driver so that impedance matching will be
maintained)?

Any information, in general, or in specific on the subject is greatly
appreciated.


Thank you.

Best Regards,

Scott Mee
Johnson Controls Inc.
Automotive Systems Group
EMC Product Compliance

616.394.2565
scott....@jci.com


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