Mark, according to the material spec, you can count with about 500 V/mil of vertical layer separation in FR4. That means you should design with a minimum of 5 mils between the Ethernet routing on the cable-side of the transformer and the adjacent planes, if you want to be on the safe side. 5 mils have never caused hipot problem in my experience. For the same reason, I also recommend a minimum of 5 mils horizontal edge-to-edge clearance on the same layer in the internal layers. On the external layers I recommend a minimum of 50 mils of edge-to-edge separation. Soldermask helps, but you shouldn't count on it. You don't need more than 75 mils on the surface layers.
Pay attention to the connector shell, which may cause high-voltage breakdown between to the Ethernet traces if these traces are routed on the top. This depends on the construction of the connector. Beware that the hipot requirement of IEEE802.3 has slightly changed in the latest, 2002 version. You need to meet 1500 Vrms with test duration of 1 min. In case the entire LAN is in the same building, and on the same power distribution, the requirement is 500 Vrms/1 min. There is no choice between AC, DC or Pulse tests any more. Neven > > Hello Group, > I have some concerns regarding Ethernet circuit design and applicable Hipot > testing. > If you have your typical 10/100 interface, you would have your RJ45 connector, > transformer and PHY chip. Let's take the simple one port interface. > According to many design guidelines , I will have Chassis Gnd plane and Digital > Gnd separated underneath a transformer. It means that RJ45 connector pins will > be surrounded > by chassis GND and will have about 20 mils separation between a pin (hole) and > CGND. As well it will be Tx/Rx traces running over the cgnd plane with only 4-5 > mil separation. > In this type of the design should I expect any Hipot test problems? (actually I > already have one, but not 100% sure why) The test is according IEEE 802.3 is > 1500V between any lead and Frame/Chassis Gnd. > Will 4 mils separation between trace and CGND be enough? or should I remove any > chassis gnd underneath the trace (but than how about the impedance?) > Any known cases, problems, suggestions, corrections will be highly appreciated. > Thanks, > Mark Gandler > > > ------------------------------------------- > This message is from the IEEE EMC Society Product Safety > Technical Committee emc-pstc discussion list. > > Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ > > To cancel your subscription, send mail to: > [email protected] > with the single line: > unsubscribe emc-pstc > > For help, send mail to the list administrators: > Ron Pickard: [email protected] > Dave Heald: [email protected] > > For policy questions, send mail to: > Richard Nute: [email protected] > Jim Bacher: [email protected] > > Archive is being moved, we will announce when it is back on-line. > All emc-pstc postings are archived and searchable on the web at: > http://www.ieeecommunities.org/emc-pstc This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] Archive is being moved, we will announce when it is back on-line. All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
