Hello Group, I have some concerns regarding Ethernet circuit design and applicable Hipot testing. If you have your typical 10/100 interface, you would have your RJ45 connector, transformer and PHY chip. Let's take the simple one port interface. According to many design guidelines , I will have Chassis Gnd plane and Digital Gnd separated underneath a transformer. It means that RJ45 connector pins will be surrounded by chassis GND and will have about 20 mils separation between a pin (hole) and CGND. As well it will be Tx/Rx traces running over the cgnd plane with only 4-5 mil separation. In this type of the design should I expect any Hipot test problems? (actually I already have one, but not 100% sure why) The test is according IEEE 802.3 is 1500V between any lead and Frame/Chassis Gnd. Will 4 mils separation between trace and CGND be enough? or should I remove any chassis gnd underneath the trace (but than how about the impedance?) Any known cases, problems, suggestions, corrections will be highly appreciated. Thanks, Mark Gandler
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