Hi Ravinder,
James's comment made me wonder about a statement you made about rise times being the same. Are you sure what you are seeing isn't the limit of your measuring technique? A broader noise spectrum may be due to a faster rise time that you are not seeing in the time domain. I too have observed that flip chips exhibit more heat-sink coupling. Also, do not rely on data sheets for these numbers, they can differ wildly. Can you alter the behavior of the chip to determine if one section of circuitry is responsible? e.g. output buffers.. Are the emissions from the whole package? do any of the signals from the ASIC leave the PWB? I recall fixing a problem with a board where the ASIC powered a front panel LED. That LED didn't rearly need the nS rise times from the ASIC. Keep posting clues... Sincerely, Derek L F Research. -----Original Message----- From: Pawson, James <james.paw...@echostar.com> To: EMC-PSTC <EMC-PSTC@LISTSERV.IEEE.ORG> Sent: Mon, Mar 24, 2014 4:46 am Subject: Re: [PSES] Higher EMI from ASIC built with new process Hello Ravinder, I wasn’t going to answer this as you were asking the experts ;) Flip chips couple very well into their heatsinks compared to older wirebond packages as the silicon is much closer to the top surface. Perhaps try grounding/decoupling the heatsink or changing to a ceramic material for diagnosis of the problem? Also, the package bond inductance will probably have reduced. You could look at increasing the decoupling, especially on any digital core and driver pins. Has the manufacturer provided updated reference schematics for the new chip? Rgds James Pawson EchoStar Europe From: ravinder.ajm...@hgst.com [mailto:ravinder.ajm...@hgst.com] Sent: 23 March 2014 01:39 To: EMC-PSTC@LISTSERV.IEEE.ORG Subject: [PSES] Higher EMI from ASIC built with new process Hi Experts, I am comparing EMI from two ASICs. Both have identical rise/fall times and signal amplitude. Yet the ASIC built with the later technology not only has significantly higher radiated emissions, but also shows much broader noise spectrum. PCB stackup and layout is identical. Please help me understand what other factors can be responsible for this anomaly. The older ASIC uses a wirebond package, whereas the new ASIC has flip chip package. Regards Ravinder Ajmani HGST, a Western Digital company 5601 Great Oaks Pkwy San Jose, CA 95119-1003 ravinder.ajm...@hgst.com - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. 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