Hi Gert, Thank you very much. your suggestion is very useful. I will definitely try it.
Regards Ravinder Ajmani HGST, a Western Digital company 5601 Great Oaks Pkwy San Jose, CA 95119-1003 ravinder.ajm...@hgst.com "ce-test, qualified testing bv - Gert Gremmen" <g.grem...@cetest.nl> 03/25/2014 01:47 AM To <ravinder.ajm...@hgst.com>, <EMC-PSTC@LISTSERV.IEEE.ORG> cc Subject RE: [PSES] Higher EMI from ASIC built with new process Hi Ravinder, Note that voltage measurements (even on a fast scope) are not what you are looking for in EMC. Only current measurements give you a good impression. You might construct you own current sensor with a tiny ferrite (3-5 mm) cut in two halves and put 3-5 winding on it. This works up to +/- 1 Gig only and needs shielding and some kind of calibration to use reliably. Some principles are shown below from our friend Ken Wyatt (also on this list): http://www.interferencetechnology.com/the-hf-current-probe-theory-and-application/ but I recommend using half a ferrite, to be able place it on a pcb trace for example. Regards, Ing. Gert Gremmen, BSc Van: ravinder.ajm...@hgst.com [mailto:ravinder.ajm...@hgst.com] Verzonden: Tuesday, March 25, 2014 3:55 AM Aan: EMC-PSTC@LISTSERV.IEEE.ORG Onderwerp: Re: [PSES] Higher EMI from ASIC built with new process Hi Derek, James, Thanks for your response. Rise time was measured with a high-bandwidth scope, so rise time measurements are being limited. It is my understanding is too that broad frequency spectrum will be the result of faster rise time. Which is why I am having hard time with this. Close-field probing shows higher noise above the die, so that could be one of the problems. The ASIC drives high-speed signals to a connector, which connect to a host through cable. I am interested in understanding the root cause of the noise occurring at very high frequency that what one would expect from the signal. Regards Ravinder Ajmani HGST, a Western Digital company 5601 Great Oaks Pkwy San Jose, CA 95119-1003 ravinder.ajm...@hgst.com Derek Walton <lfresea...@aol.com> 03/24/2014 06:08 AM Please respond to Derek Walton <lfresea...@aol.com> To EMC-PSTC@LISTSERV.IEEE.ORG cc Subject Re: [PSES] Higher EMI from ASIC built with new process Hi Ravinder, James's comment made me wonder about a statement you made about rise times being the same. Are you sure what you are seeing isn't the limit of your measuring technique? A broader noise spectrum may be due to a faster rise time that you are not seeing in the time domain. I too have observed that flip chips exhibit more heat-sink coupling. Also, do not rely on data sheets for these numbers, they can differ wildly. Can you alter the behavior of the chip to determine if one section of circuitry is responsible? e.g. output buffers.. Are the emissions from the whole package? do any of the signals from the ASIC leave the PWB? I recall fixing a problem with a board where the ASIC powered a front panel LED. That LED didn't rearly need the nS rise times from the ASIC. Keep posting clues... Sincerely, Derek L F Research. -----Original Message----- From: Pawson, James <james.paw...@echostar.com> To: EMC-PSTC <EMC-PSTC@LISTSERV.IEEE.ORG> Sent: Mon, Mar 24, 2014 4:46 am Subject: Re: [PSES] Higher EMI from ASIC built with new process Hello Ravinder, I wasn’t going to answer this as you were asking the experts ;) Flip chips couple very well into their heatsinks compared to older wirebond packages as the silicon is much closer to the top surface. Perhaps try grounding/decoupling the heatsink or changing to a ceramic material for diagnosis of the problem? Also, the package bond inductance will probably have reduced. You could look at increasing the decoupling, especially on any digital core and driver pins. Has the manufacturer provided updated reference schematics for the new chip? Rgds James Pawson EchoStar Europe From: ravinder.ajm...@hgst.com [mailto:ravinder.ajm...@hgst.com] Sent: 23 March 2014 01:39 To: EMC-PSTC@LISTSERV.IEEE.ORG Subject: [PSES] Higher EMI from ASIC built with new process Hi Experts, I am comparing EMI from two ASICs. Both have identical rise/fall times and signal amplitude. Yet the ASIC built with the later technology not only has significantly higher radiated emissions, but also shows much broader noise spectrum. PCB stackup and layout is identical. Please help me understand what other factors can be responsible for this anomaly. The older ASIC uses a wirebond package, whereas the new ASIC has flip chip package. Regards Ravinder Ajmani HGST, a Western Digital company 5601 Great Oaks Pkwy San Jose, CA 95119-1003 ravinder.ajm...@hgst.com - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. 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