Hi Amund/Gert,

I agree with Gert’s advice, that all (especially high speed) signal layers need 
to have an adjacent ground return plane in order to properly capture the 
electromagnetic wave of the digital signals (which travel in the dielectric 
space between layers). The one exception, in my view, would be that we need the 
same adjacent return for power. Here’s my reasoning:

1. With all the digital switching and corresponding transients occurring, power 
rails (and planes) are also transmission lines.
2. The electromagnetic waves from these power rail transients travel through 
the dielectric space between the power rail and the nearest metal (adjacent 
layer).
3. Therefore, to avoid power transient coupling to other signal layers, there 
must be an adjacent return plane for every power plane (or routed / polygon) 
power.
4. Making the power and return planes adjacent and close together will also 
enhance high frequency decoupling.

That is, placing a signal layer between power and power return can couple 
switching transients to that signal layer.

I wrote a four-part series on PC board design to minimize EMI that may help. I 
discuss in more detail how digital signals move in boards, good and bad 
stack-ups, and partitioning of circuits to avoid coupling. Hope it helps 
clarify the physics.

https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/ 
<https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/>

Cheers, Ken

_______________________

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help!

Kenneth Wyatt
Wyatt Technical Services LLC
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> On Feb 10, 2020, at 2:29 AM, Gert Gremmen <g.grem...@cetest.nl> wrote:
> 
> It s an extra layer you might allocate to that low frequency signals , analog 
> signals and or extra power supply.
> 
> On 10-2-2020 10:22, Amund Westin wrote:
>> Thanks Gert
>>  
>> I want to read your advices with great attention. 
>> Just one immediately follow-up èThis Misc layer, is it an extra layer for 
>> signal routing, as a Sbott3?
>>  
>> Mvh Amund
>>  
>>  
>> Fra: Gert Gremmen 
>> Sendt: 10. februar 2020 09:57
>> Til: Amund Westin <am...@westin-emission.no> 
>> <mailto:am...@westin-emission.no>; EMC-PSTC@LISTSERV.IEEE.ORG 
>> <mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
>> Emne: Re: [PSES] PCB layout technique - multilayer
>>  
>> Just 2 hints of thousands:
>> 
>> If you implement 2 ground planes make sure the ground references on top and 
>> bottom are related to the closest ground layer .
>> 
>> The stack will than be:  Stop -- GND --Stop2 -- PWR - Misc - Sbott2 - GND 
>> -Sbott     ((S=signal)) 
>> 
>> (basically you route 2 x 3 layer boards critically, and bond them together 
>> with a power plane in between.)
>> 
>> The signal should not cross the board and be tempted to flow on an opposite 
>> ground layer, but
>> 
>> will remain always close to the corresponding ground layer.    
>> 
>> Make sure both ground layers are extremely well coupled together, esp on 
>> board edges 
>> 
>> If you implement SMPS locally give it a local top layer ground area to 
>> connect the principal
>> 
>> switch elements together. Connect by a dice pattern 5 via to main GND
>> 
>> Good luck.
>> 
>> Gert Gremmen
>> 
>> On 10-2-2020 8:27, Amund Westin wrote: contact to the nearest ground layer,
>>  
>>  
>> I’m looking for articles about how to do good EMC layout on multilayer PCB.
>> Choice of PCB layer stacking (8 or 10 layers) and basic routing techniques 
>> are the issues of most importance right now.
>> Appreciate if you have some experience about good or bad layer stacking.
>>  
>> Thanks!
>>  
>> Best regards
>> Amund 
>>  
>>  
>>  
>>  
>>  
>> -
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> <g_gremmen.vcf>


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