Peter C. Wallace wrote: > > I've been thinking about a related problem with our RS-422 serial > interfaced Amps and controllers, and the general problem of using the > hardware > for more precise timing, but leaving EMC in control of timing. > > With a FPGA, its possible to make a hardware timer thats phase locked > to EMCs servo thread, basically just a DDS that the thread reads at 'time 0' > This read has two functions, > > 1. The value read is the current timer mismatch with EMC thread, which tells > you whether you are 'locked' > > 2. A hardware side effect of the read is to tweak the DDS to (slowly) correct > the mismatch. > > Once the DDS is locked, the DDS accumulater bits can be compared with > a list of timer values in FPGA memory (> compare), allowing hardware actions > to be taken and any desired "phase angle" during the servo thread period. > This > way for example, our outgoing serial packets can have jitter in the nS range, > or a PPMC card connected to a FPGA created EPP port could have read-ahead > done > just before the data is required... A VERY interesting concept!
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