Snip_________________________________________________________________
> Wellll - not quite.
> Unless they use the same clock source, there will be skew. Every once
> in a while, you'll get two packets in a single servo period, or you'll
> get none. That doesn't even take into consideration the jitter you get
> on the PC end, which will cause the same problem even if you do have a
> common clock source. You either need a request/response system, or you
> need the remote unit to update frequently enough that the data isn't too
> stale no matter when you read it. For example, if you have a 1ms
> period, and 25 us old data is "close enough", then send packets at 4 or
> 5 KHz, and the data can never be more than 25 or 20 us old. Of course,
> you then need some way of marking a set of data as complete (so HAL can
> read from it) and as "in use" (so the net driver doesn't write to it) -
> all of that non-blocking ...
I've been thinking about a related problem with our RS-422 serial
interfaced Amps and controllers, and the general problem of using the hardware
for more precise timing, but leaving EMC in control of timing.
With a FPGA, its possible to make a hardware timer thats phase locked
to EMCs servo thread, basically just a DDS that the thread reads at 'time 0'
This read has two functions,
1. The value read is the current timer mismatch with EMC thread, which tells
you whether you are 'locked'
2. A hardware side effect of the read is to tweak the DDS to (slowly) correct
the mismatch.
Once the DDS is locked, the DDS accumulater bits can be compared with
a list of timer values in FPGA memory (> compare), allowing hardware actions
to be taken and any desired "phase angle" during the servo thread period. This
way for example, our outgoing serial packets can have jitter in the nS range,
or a PPMC card connected to a FPGA created EPP port could have read-ahead done
just before the data is required...
Peter Wallace
Mesa Electronics
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