Sebastian, The enable pin for the PWM is getting set. If I set the enable to true, and then set the value to say 5.0, when I do a show pin I do in fact see that the enable pin is true and that the pwm value pin is 5.0.
Per your other email, I would think that this also proves that the scale is set correctly. It is set to 1.0 in the ini file. I don't have access to the machine at the moment, but I will check these again as soon as I can get back to the machine. Regards, Eric The PWM DDR register is set to 65535 on module load and then left alone. The PWM output type defaults to 1 (PWM + Dir), though the user can change it to 2 (Up + Down) by setting the output-type parameter. The pwmgen.XX.enable HAL pin gets initialized to 0 and sent to the FPGA on module load. When the user changes the HAL pin, the new value is sent to the FPGA. Eric, can you verify that the HAL enable pin for the PWM in question does get set to 1? ------------------------------------------------------------------------- This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK & win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100&url=/ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
