Peter C. Wallace wrote: > Can you verify that your parallel port supports and is configured for EPP > version 1.9 (1.7 will _not_ work) > > After a little thinking, your symptoms (parallel port firmware load works but > communication with FPGA fails) suggests the possibiolity that your EPP port > is > in 1.7 mode...
I dont understand this. The difference between EPP 1.7 and 1.9 is that in 1.7, a sender can start a new Data cycle before the receiver asserts nWait indicating the end of the current cycle, but in 1.9 the sender has to wait, right? I assume the 7i43 CPLD and HostMot2 both implement EPP 1.9, meaning they always respect nWait when sending data. If the BIOS sets the EPP controller on the PC to EPP 1.7 mode, then that means that the PC might send data to the 7i43 faster than the 7i43 is prepared to accept it (the PC would start the next Data cycle before the 7i43 asserted nWait). It seems to me that this problem would be exacerbated if the PC had a lot of data to send, such as during firmware loading. But firmware loading is the one thing that seems to work (as evidenced by the /INIT bit doing the right thing); it's the subsequent read from the 7i43 that's problematic. But the read from the 7i43 should be controlled by the EPP 1.9 compliant timing in the 7i43. What am I missing? -- Sebastian Kuzminsky Distances obtained as the speed of light multiplied by a cosmological time interval have no direct physical significance. <http://en.wikipedia.org/wiki/Observable_universe> ------------------------------------------------------------------------- This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK & win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100&url=/ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
