On Jan 4, 2009, at 3:56 PM, Jon Elson wrote: > Dave Engvall wrote: >> <snip> >> since I didn't find Jon's post on the interrupt process. >> >> >> Some reading of pdp wiki, etc refreshes memory (slowly). >> >> There were 4 interrupt lines which gave only 4 levels of interrupt. >> Then interrupts were further arbitrated by the position of the >> interrupting board on the bus. >> >> > This is only the interrupt priority LEVELS. There were 4 priority > chains for asking for an interrupt. > But, the full address/data bus (on Q-bus) was available for the > vector. > (Various CPUs would accept so many bits as the vector address.) > > Jon
I think we are actually on the same page. I did not mean to imply that there were only 4 interrupts. Because of the daisy-chaining of interrupts down the bus each board essentially had it's own interrupt and the only way to run out of interrupts was to fill the interrupt stack space. The elegance of this scheme is concealed by its simplicity. Dave > > ---------------------------------------------------------------------- > -------- > _______________________________________________ > Emc-users mailing list > Emc-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/emc-users ------------------------------------------------------------------------------ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
