On Sun, 4 Jan 2009, Gene Heskett wrote:
> Date: Sun, 04 Jan 2009 01:16:18 -0500
> From: Gene Heskett <gene.hesk...@gmail.com>
> Reply-To: "Enhanced Machine Controller (EMC)"
> <emc-users@lists.sourceforge.net>
> To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
> Subject: Re: [Emc-users] OT: PDP11
>
> On Sunday 04 January 2009, Peter C. Wallace wrote:
>> uOn Sat, 3 Jan 2009, Gene Heskett wrote:
>>
>> SNIP_______________
>>
>>> As a matter of fact, yes. The quad core amd phenoms, (I have a slow one
>>> in this box) with some additional controls in the kernel to release one
>>> core just for the realtime stuff, and then hand that core to rtai, seems
>>> like it might be a pretty ideal situation. The only latency problem I
>>> could see would be in freeing up the buss when it needs to access the
>>> parport, some method of freezing the other 3 cores in their tracks for a
>>> couple of cpu cycles might have to be worked out.
>>>
>>> Either that, or do a 'propeller' board for that part, in which case the
>>> base loop could probably go away.
>>>
>>> I've been looking at that chip since it came out, has anyone here played
>>> with it yet?
>>
>> A perhaps more interesting chip for current "hardware replaced by software"
>> designs is the 4 core XMOS (XS1-G4) with 4x 400 MHz cores each with 8
>> hardware contexts, about $20 for 1 piece (144 pin) and a $99 devkit. Kind
>> of Ubicom on steroids...
>
> Sounds interesting, but will it be around 10 years from now? I don't think
> that is too unreasonable even if I might not be. We do have chip makers
> checking in now & then with 25 year old stuff, and it seems hard enough to
> convince the folks using older emc versions to get current versions installed
> cuz you fixed that bug 2 years ago. They don't want to contemplate the loss
> of money that an extended downtime debugging a newer version might entail.
>
>> On the other hand you can do a lot with a embedded 32 bit processor in a
>> FPGA (the ZPU for example uses about 20% of a 400K SP3, runs at ~ 100 MHz,
>> is BSD licensed and has a GCC toolchain)
>
> Which again, sounds like a plus till you said 100mhz. That might do for servo
> driven machines but I'd guess it won't run steppers at usable speeds will it?
Of course the FPAG woudl have hardware step generation as well, but actually a
100 MHz processor with decent I/O even without hardware step generation will
make steps just fine (1 MHz interrupt rates are no problem at all)
You are comparing this to a PC which has dreadful real time performance (Great
throughput but poor latency). On our little test 32 bit CPU a 32 bit output
takes 1 instruction (10 ns). Try that on a PC...
SNIP_____________________________________________________
Peter Wallace
Mesa Electronics
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