Jon Elson wrote: >John Kasunich wrote: > > >>Be careful here. You must ensure that the count and the timestamp are >>from the SAME encoder edge. That's why I like stuffing both values into >>the same wide register. There are certainly other ways to ensure the >>same result. You already deal with that problem when reading your 24 >>bit count registers over the 8 bit EPP bus, now you have 40 bits to deal >>with. >> >> >> >> >Ah, good point! So, not only is there the timestamp storage register, >but it needs a holding register (per axis) that is clocked when the >encoder latch register is clocked. Tha doesn't sound real hard to do. > > You've already got 24 bits per counter, you might be able to get by with just splitting that into a 12-bit counter and a 12-bit timestamp. Use a 1MHz or even 250 or 500 kHz timer (though 1 MHz would still take 2 or 4 ms to overflow). The input would have to be getting a 2MHz+ edge rate to overflow in the default 1 kHz servo cycle.
I saw that the top 16 read registers are unused also, so you could just add 8 bytes there with 16-bit timestamps. Another option is to use the top 16 bytes as four, 4-byte registers with 16+16 bit count+timestamp data. If there's a version check, the read region can be set up to read from 0x0C through 0x1F instead of 0x00 - 0x0F. This keeps the read contiguous, and only adds 4 bytes to the data size. - Steve ------------------------------------------------------------------------------ This SF.net email is sponsored by: High Quality Requirements in a Collaborative Environment. Download a free trial of Rational Requirements Composer Now! http://p.sf.net/sfu/www-ibm-com _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
