On 23 October 2010 13:58, Andy Ibbotson <andyi_w...@btinternet.com> wrote:
>
> Thanks Andy.  I thought that EMC2 required EPP mode on the parallel port

AFAIK only for devices that use it for communications, not for
applications which simply twiddle the pins on and off as individual
signals. I might be mistaken.

> think people are using the board to drive software stepgen.

Yes, it has a nice low latency which suits that.

> Going back to the PCI based cards, does the extra speed of the interface
> mean that the servo thread can be run faster giving increased update rates
> of velocity?

Possibly. I have read somewhere that a sane (200uS) servo-thread
_execution_ period is only enough time to shift 50 bytes through a
parallel port. That is potentially limiting, but has not been a
problem I have noticed with my 4-axis machine. The software stepgens
running in the base thread and twiddling pins individually are
effectively shifting one word per thread cycle.

>  I'm trying to assess the benefits of moving from software
> stepgen to hardware stepgens.

The main "win" is possibly fast encoder counting for spindle encoders.
The advantage from a stepgen point of view is reduced granularity of
step timings at higher rates. with a 20uS base thread you hit the
point where your step time gets quantised into 80uS, 60uS, 40uS or
20us (with x8 microstepping and 200ppr that's 470rpm, 625rpm, 940rpm
and 1880rpm) and you are effectively asking your motor to
instantaneously accelerate between the speeds which is asking a lot of
a motor which is probably already running out of torque a those
speeds.

Another huge advantage is that suddenly you have GPIO pins in abundance.

-- 
atp

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