Hi, Some info about the FPGA boards on my site: At this point, the FPGA boards I have listed don't have any released software support to go with them. I'm going to work on making a library for simple I/O. This version of the board uses the same BBB I/O pins that Charles's MachineKit uses for STEP/DIR, etc. as I had read negative comments on the internet about using the BBB's eMMC data path. Thus the data/control to the FPGA is currently done with "bit-bang" type control. To mask all of that I'll simply have a library with 4 basic functions: SelectRead and SelectWrite which set an address and do a byte read or write. Then there would be the ReadMore and WriteMore type functions which get/set the next byte using auto increment feature built in to FPGA firmware. I have all of this tested and working so far. These are used to have a psuedo simulation of a PC EPP parallel port. This basically means address register read/write and data register read/write, with auto increment on the data register R/W using 8 data bits, and 4 control lines (ASTROBE, DSTROBE RD_WRn and RDY).
I've also written a small program that will take a Xilinx BIN file and dump it to the FPGA to program that device. The software manipulates the bytes individually so no "bit swapping" is necessary. This version of board does not read any data stream out of the FPGA it simply dumps the firmware data to the FPGA and waits for the DONE to be properly set. Programing of the FPGA firmware using the BBB is very quick (much faster than my parallel port JTAG progamming port). At first I attempted to configure the setup with Hostmot2 and hm2_7i43 software. After a bit I was able to get both hostmot2 and hm2_7i43 working on the BBB side. Then I started looking in to the FPGA side and had to back off (whoa!). While I was able to get that whole suite to compile for the X9 part I couldn't run it properly. I think that there are some differences that might need changing, for example the X9 does not use the DCM like the Spartan3 series does (though it interestingly enough compiled). There may be some other dialects between parts that need a bit of code modification as well; I was seeing warning about how RAM blocks were being used. As mentioned, I decided to back off, so what I did next was to modify the PPMC code. I've written a simple VHDL program to generate the encoders and PWM registers to do some simple tests. Using Hostmot/7i43 might be a final solution, but I'm still learning the way LinuxCNC (and Linux in general) works. Anyway, right now I'm adapting the PPMC software to work with a small I/O board I made. As can be seen on my web pages, the FPGA board has two 50-pin IDC headers, each with 24 pins of I/O from the FPGA. These signals are routed through FET bus switches, which are enabled with the MachineKit BB_IO_RDY# signal. All FPGA I/O must be 3.3V logic (no 5V at all). Each signal has a GND pin associated with it (pin 1-signal, pin 2-GND, and so on, with pin 49 being 3V3 and pin 50 again GND). I've made a mating I/O board that uses one of these ports. The I/O board routes a FPGA signal past a diode from GND to signal,and from signal to 3.3V, then through a 47 ohm resistor to be used on-board. The I/O board has 4 encoder set ports (singled ended A, B, I, 5V and GND on each of the four) which are RC buffered and logic level shifted through LVC541 buffers. It also has four discrete inputs set per axis (16 total discrete inputs on four 6-pin headers). It also has 4 outputs ports (Signal A, Signal B and an ENA# signal, along with 5V and GND). The Signal A and B could be used for STEP/DIR or PWM/DIR. The ENA# is common to all four ports. These outputs are driven by LVC06, open collector buffers to the 5 pin headers (5V S1, S2, ENA#, GND). I also have a single 10 pin header with 8 discrete output signals on it also buffered through LVC06's. 7 main outputs lines, and the same ENA# that is used on the other outputs. The discrete I/O are sent SPI fashion from the FPGA to the I/O board which has a XC2C64A CPLD to do translation. This allowed my to have all of the I/O and still only use the 24 pins available on one port of the FPGA board. Anyone who's interest can see a quick photo of the I/O board mentioned here: http://xylotex.netfirms.com/OSCommerce/catalog/product_info.php?cPath=27&products_id=64 I hope to have the I/O board and firmware on the FPGA board talking with the modified PPMC software some time before the daylight savings time kicks in. Jeff ---------------------------------------- > Date: Tue, 25 Feb 2014 07:45:42 -0600 > From: josiahmor...@gmail.com > To: emc-users@lists.sourceforge.net > Subject: [Emc-users] beaglebone fpga with linuxcnc > > I noticed that xylotex has an fpga cape in the works for beaglebone black. > (as well as other similar items from other sources) > I was curious if anyone was looking into the implementation of such fpga > capes into a linuxcnc build. > also, what would be the benefits and drawbacks to the addition of this fpga > module? > has anyone thought about how linuxcnc would be able to actually take > advantage of the fpga capabilities? > I'm just curious because I could see some benefits of possibly allowing the > fpga to house the kinematics functions as well as drive multiple step pins > simultaneously. I just don't know how linuxcnc would command it. > anyway, I just wanted to bring this up for discussion and see what thoughts > people had on it. > > thanks. > > -- > Josiah Morgan, P.E. > ------------------------------------------------------------------------------ > Flow-based real-time traffic analytics software. Cisco certified tool. > Monitor traffic, SLAs, QoS, Medianet, WAAS etc. with NetFlow Analyzer > Customize your own dashboards, set traffic alerts and generate reports. > Network behavioral analysis & security monitoring. All-in-one tool. > http://pubads.g.doubleclick.net/gampad/clk?id=126839071&iu=/4140/ostg.clktrk > _______________________________________________ > Emc-users mailing list > Emc-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/emc-users > ------------------------------------------------------------------------------ Flow-based real-time traffic analytics software. Cisco certified tool. Monitor traffic, SLAs, QoS, Medianet, WAAS etc. with NetFlow Analyzer Customize your own dashboards, set traffic alerts and generate reports. Network behavioral analysis & security monitoring. All-in-one tool. http://pubads.g.doubleclick.net/gampad/clk?id=126839071&iu=/4140/ostg.clktrk _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
