On 27 February 2015 at 22:24, Brent Loschen <[email protected]> wrote: > If so, what is that data and how is it different from step/dir signals > in the default case? Can anyone comment on the differences or point me > to documentation that explains it?
It might help to start with the parport stepgen. That has two functions. The slow function runs every time the servo-thread runs, typically every 1mS. It reads in the next position target from HAL, looks at where it is now, and calculates a step-rate required to get to that position by the time the next update comes in in 1mS. Then the base-thread runs about every 25uS and either makes a pulse or doesn't make a pulse depending on whether one is needed to maintain the step rate requested by the servo thread. In the case of a Pico or Mesa p-port connected FPGA card the first step looks just the same. Code running on the PC looks at position and target and decides what step-rate is needed. But this data is then passed to the FPGA as data on the EPP bus, and the actual steps are generated by the FPGA. The big difference is step-rate resolution. The "base clock" of the bit-banged solution is 25kHz. The FPGA card timer resolution is around 10Mhz. -- atp If you can't fix it, you don't own it. http://www.ifixit.com/Manifesto ------------------------------------------------------------------------------ Dive into the World of Parallel Programming The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
