> From: Peter Blodow [mailto:p.blo...@dreki.de]
> Yeah, and these "skewy" bits were the reason why in the days of parallel
> bus connections all operations had to be acknowledged on separate wires
> so it was made sure the bits had arrived correctly. This made
> connections slow, but terribly reliable. The DEC computer series like
> the VAXes were an example. This reliability was given up for the sake of
> speed, but at the same time, useless games becoming dominant in the
> computer world, it did not matter any more.
> 
> Peter

So true, even with PCs.  The buses may be serial but eventually the data
ends up parallel again.   Way back in the early 90's we were working with a
CAN bus ISA card.   The PC sent CAN messages to all the remote nodes to
operate the machine.  Every once in a while there was a glitch.  

It was a year later when I was writing NT 3.51 device drivers that I
stumbled onto the actual problem.  The commands were transferred via ISA bus
into a FIFO on the card.  They used an FPGA for all the address translation
and signalling for latching data.  There were occasions where the rising
edge of a signal was a tad late.  We're talking nano-seconds.  That would
result in the wrong data being latched into the FIFO and the wrong command
would  be sent.  I think the delay was in the order of a single gate
transition time so all the engineer did was add a non inverting buffer  in
series with the signal for the odd (or maybe it was the even) byte and the
problem was fixed.  This was on 386 PCs so they weren't blindingly fast.

With the popularity of ARM cores inside FPGA's and the the encoder/drive
signals done in VHDL the parallel problem hasn't really gone away.  Just
harder to find.

John Dammeyer





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