They put a Cortex M0 on the module that sits on the board, along with the 
stepper driver and encoder.

There's a greater latency inside the Cortex, it will likely have to respond to 
an interrupt thus have ISR latency.  I presume they've got a PLL to prevent 
oscillation within the final step.

It's not a bad case for an FPGA, since with proper coding the latency is 
limited by the response time of the transistors.

Danny


---- Nicklas Karlsson <nicklas.karlsso...@gmail.com> wrote: 
> Best option is probably to generate stepper signal from hardware timer.
> 
> 2016-10-21 8:17 GMT+02:00 Danny Miller <dan...@austin.rr.com>:
> 
> > The SPI comm of course has latency within a comm period.
> >
> > However, the pulse output must be super-fast.  It supports up to 14500
> > rpm, so if it's 2000steps/rev the whole step cycle is 2ms, realistically
> > like maybe 1/4 of that for latency?
> >
> > Danny
> >
> > On 10/19/2016 11:34 PM, Nicklas Karlsson wrote:
> > >>> ... The lag also seemed to vary with velocity.
> > >>>
> > >>>
> > >> Most specifically, it was a lag in the encoder's loop to respond to
> > >> acceleration.
> > >> Velocity was fine, but when there is acceleration, the encoder's
> > >> velocity didn't change for a few milliseconds, then it had to produce
> > >> velocity greater than real for position to catch up.
> > >> I thought it was a really severe problem, but it seems it may not be all
> > >> that bad.  But, it can make servo tuning more tricky.
> > >>
> > >> Jon
> > > Delay is called phase in control theory and it is not good at all for
> > fast response.
> > >
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