Hello! I've been testing 7i80 (7i80hd_16_svst1_4_7i47s.bit) with 7i47S. According to the manual and hm2 load report I should have stepgen0..3 at TX0...TX7 outputs. But what I seem to have is stepgen0..1 at TX4...7, stepgen2..3 is at TX0..3. This is pretty confusing. Or am I missing something?
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