On Sat, 25 Apr 2020 at 01:03, David Berndt <ber...@uberwin.com> wrote:

> Feels a bit unsatisfying though. I understand the timing issues (though
> I'm not sure with a slow homing cycle I should care) but not solving this
> in a reasonably elegant way in software seems like a fail to me.

To solve it _properly_ in the software you would need to solve it in
the FPGA software.

I don't think you need to worry about common grounds. If  each encoder
index can drive the Z inputs of one channel on the 7i77 it can drive
the Z input of two of them.
(Though if they are wired as differential inputs I am not sure if you
would go with parallel or serial)

I guess that the linear scale pulse is the one to use.

-- 
atp
"A motorcycle is a bicycle with a pandemonium attachment and is
designed for the especial use of mechanical geniuses, daredevils and
lunatics."
— George Fitch, Atlanta Constitution Newspaper, 1912


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