On Wednesday 21 October 2020 20:21:30 Peter C. Wallace wrote: [...] > >>>>>> sudo mesaflash --device 5i25 --readhmid > >>>>> > >>>>> gene@GO704:~/linuxcnc$ sudo mesaflash --device 5i25 --readhmid > >>>>> [sudo] password for gene: > >>>>> Configuration Name: HOSTMOT2 > >>>>> > >>>>> General configuration information: > >>>>> > >>>>> BoardName : MESA5I25 > >>>>> FPGA Size: 9 KGates > >>>>> FPGA Pins: 144 > >>>>> Number of IO Ports: 2 > >>>>> Width of one I/O port: 17 > >>>>> Clock Low frequency: 33.3333 MHz > >>>>> Clock High frequency: 200.0000 MHz > >>>>> IDROM Type: 3 > >>>>> Instance Stride 0: 4 > >>>>> Instance Stride 1: 64 > >>>>> Register Stride 0: 256 > >>>>> Register Stride 1: 256 > >>>>> > >>>>> Modules in configuration: > >>>>> > >>>>> Module: WatchDog > >>>>> There are 1 of WatchDog in configuration > >>>>> Version: 0 > >>>>> Registers: 3 > >>>>> BaseAddress: 0C00 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Module: IOPort > >>>>> There are 2 of IOPort in configuration > >>>>> Version: 0 > >>>>> Registers: 5 > >>>>> BaseAddress: 1000 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Module: QCount > >>>>> There are 2 of QCount in configuration > >>>>> Version: 2 > >>>>> Registers: 5 > >>>>> BaseAddress: 3000 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Module: SSerial > >>>>> There are 1 of SSerial in configuration > >>>>> Version: 0 > >>>>> Registers: 6 > >>>>> BaseAddress: 5B00 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 64 bytes > >>>>> > >>>>> Module: PWM > >>>>> There are 2 of PWM in configuration > >>>>> Version: 0 > >>>>> Registers: 5 > >>>>> BaseAddress: 4100 > >>>>> ClockFrequency: 200.000 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Module: StepGen > >>>>> There are 9 of StepGen in configuration > >>>>> Version: 2 > >>>>> Registers: 10 > >>>>> BaseAddress: 2000 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Module: LED > >>>>> There are 1 of LED in configuration > >>>>> Version: 0 > >>>>> Registers: 1 > >>>>> BaseAddress: 0200 > >>>>> ClockFrequency: 33.333 MHz > >>>>> Register Stride: 256 bytes > >>>>> Instance Stride: 4 bytes > >>>>> > >>>>> Configuration pin-out: > >>>>> > >>>>> IO Connections for P3 > >>>>> Pin# I/O Pri. func Sec. func Chan Pin func > >>>>> Pin Dir > >>>>> > >>>>> 1 0 IOPort StepGen 0 Dir/Table2 > >>>>> (Out) 14 1 IOPort StepGen 0 > >>>>> Step/Table1 (Out) 2 2 IOPort StepGen 1 > >>>>> Dir/Table2 (Out) 15 3 IOPort StepGen > >>>>> 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 > >>>>> Dir/Table2 (Out) 16 5 IOPort StepGen 2 > >>>>> Step/Table1 (Out) 4 6 IOPort StepGen 3 > >>>>> Dir/Table2 (Out) 17 7 IOPort StepGen 3 > >>>>> Step/Table1 (Out) 5 8 IOPort StepGen 4 > >>>>> Dir/Table2 (Out) 6 9 IOPort StepGen 4 > >>>>> Step/Table1 (Out) 7 10 IOPort SSerial 0 > >>>>> TXData1 (Out) 8 11 IOPort SSerial 0 > >>>>> RXData1 (In) 9 12 IOPort SSerial 0 > >>>>> TXData2 (Out) 10 13 IOPort SSerial 0 > >>>>> RXData2 (In) 11 14 IOPort QCount 0 > >>>>> Quad-IDX (In) 12 15 IOPort QCount 0 > >>>>> Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) > >>>>> > >>>>> IO Connections for P2 > >>>>> Pin# I/O Pri. func Sec. func Chan Pin func > >>>>> Pin Dir > >>>>> > >>>>> 1 17 IOPort StepGen 5 Dir/Table2 > >>>>> (Out) 14 18 IOPort StepGen 5 > >>>>> Step/Table1 (Out) 2 19 IOPort StepGen 6 > >>>>> Dir/Table2 (Out) 15 20 IOPort StepGen > >>>>> 6 Step/Table1 (Out) 3 21 IOPort StepGen 7 > >>>>> Dir/Table2 (Out) 16 22 IOPort StepGen 7 > >>>>> Step/Table1 (Out) 4 23 IOPort StepGen 8 > >>>>> Dir/Table2 (Out) 17 24 IOPort StepGen 8 > >>>>> Step/Table1 (Out) 5 25 IOPort PWM 0 PWM > >>>>> (Out) 6 26 IOPort PWM 0 /Enable (Out) > >>>>> 7 27 IOPort PWM 0 Dir (Out) 8 28 > >>>>> IOPort SSerial 0 TXData3 (Out) 9 29 IOPort > >>>>> SSerial 0 TXEn3 (Out) 10 30 IOPort > >>>>> SSerial 0 > >>>>> RXData3 (In) 11 31 IOPort QCount 1 > >>>>> Quad-IDX (In) 12 32 IOPort QCount > >>>>> 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-A > >>>>> (In) > >>>>> > >>>>> gene@GO704:~/linuxcnc$
> >>>> Yep that looks like a 7I76+7I78 configuration > >>>> with just one PWMGen for the 7I78 on P2 > >>> > >>> but this is the load line that generated that dmesg: > >>> loadrt hm2_pci config="num_encoders=2 num_pwmgens=2 > >>> num_stepgens=3" > >> > >> Thats a pinout file not a dmesg log > > > > Its the output of the --readhmid command you asked for. I just copy > > pasted it all, including the mesaflash command you can see at the > > top of the paste. > > > > the dmesg file shows the 2nd pwmgen, but the dir signal is > > permanently grounded. Thats with the original 5i25_7i76_1px2d.bit file installed. > Um no, there is only PWM 0 brought out > What pin is grounded? > P2-05. With either bitfile installed, 3 5i25's tested. > >> It does seem to have a harmless inconsistency > >> (2 PWMgen inside but only 1 wired to the output) Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) If we desire respect for the law, we must first make the law respectable. - Louis D. Brandeis Genes Web page <http://geneslinuxbox.net:6309/gene> _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
