Bob Colwell,
Hello! My name is Brent Rogers and I am a recruiter in Dallas, Texas. I am
presently doing a search for candidates with x86 experience. Please take a
look at the openings below and let me know if you are interested or if you
know someone that might be interested.
Thanks in advance,
Brent Rogers


OPENINGS--------

Sr. MTS Design Engineer/Technical Lead, Functional Verification

Location
Sunnyvale, CA or Austin, TX

Salary
$140,000 - $165,000

Description
As a technical lead for their product line, you will be developing the
functional verification strategy for complex state-of-the-art microprocessor
designs. Provide technical expertise and strategic direction for developing
the functional verification strategy for current and next generation
microprocessor designs. Maintain and enhance existing functional
Verification methodology. Improve existing infrastructure. Work on related
projects and/or
assignments as needed, to meet team goals. Act as a project leader on
specific projects and provide leadership and guidance to junior engineers in
the team. Perform project definition, training and documentation. Develop
quality, timely and cost effective solutions, very independently. Interface
with architects and CMD/TMD RTL/logic designers. Develop an effective
working relationship with parties involved.
QUALIFICATIONS: A technology related Bachelor's degree or equivalent
combination of training and experience with 5+ years of related experience.
A Master's degree with 3+ years of related
experience or a doctorate degree is preferred. Requires demonstrated
technical expertise in functional verification of microprocessor designs.
Experience with Verilog HDL, programming in Perl, C/C++ and UNIX, logic
simulation is a requirement. Direct experience with Verilog simulators is a
plus. Requires good understanding of computer architecture and assembly
programming.



Develop environments for stand alone block level functional validation and
help debug and correct functional errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth
understanding of the architecture and HDL/logical design of the
microprocessor. Develop an automated regression infrastructure setup for
functional verification of high-speed microprocessor designs. Develop/run
directed tests for current and new x86 instructions and develop/use random
exercisers, to validate functionality of microprocessor designs.

Preferred Education and Experience
BS and 7+ years experience, MS and 5+ years experience, or PhD and 1+ years
experience desired.



Sr. Logic Design Engineer/Lead

Location
Sunnyvale, Ca

Salary
$150,000 - $170,000

Description
Lead a small team of designers responsible for high-speed logic design and
physical implementation of this next generation high-performance X86
microprocessor. Would also be expected to own/drive global issues such as
chip timing, chip integration, global electrical issues, and the design
methodology.

Expertise in microprocessor design, high-speed logic design, custom place
and route, and timing analysis is required. Good management skills are
desired. Good working knowledge of verilog, vendor CAD tools for gate-level
verification, timing analysis, electrical analysis and physical design.
Knowledge of various circuit issues such as signal coupling/noise is
desired. Experience with methodology definition and development, and tool
scripting (example Perl) are desired. Solid knowledge of computer
architecture and circuit design/analysis is preferred.

A minimum of BS in engineering and 9+ years or MS in engineering and 7+
years of related experience including leading teams in high speed
microprocessor logic and physical design. Preferred experience in driving
global projects and strong skills in microarchitecture.

Brent Rogers, President
Rogers Recruiting
972-818-9675 Phone
972-713-8051 Fax
[EMAIL PROTECTED]
www.RogersRecruiting.com
"We are matching great people to great opportunities!"


_______________________________________________
Finale mailing list
[EMAIL PROTECTED]
http://mail.shsu.edu/mailman/listinfo/finale

Reply via email to