On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote: > Misha Manulis asked for satasii support on PPC and on IRC we gave him > some hints to hack up something that works for ppc only and satasii > only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA > > Here is a patch which does everything The Right Way (TM) and uses proper > abstraction for satasii and compiles all x86 specific stuff only on x86. > > Huge thanks go to Segher Boessenkool who provided valuable info about > all the endianness trickery (especially preprocessor macros) and tested > 8 iterations of the code on Linux/PPC. > > On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote: > >> flashrom is very x86 centric. It does work on other architectures if you >> get it to compile. Try to fix the all errors on ppc for a >> full build. >> >> Should work in theory with a default build if you exclude nic3com. >> Will pretty sure break compilation on Alpha. >> >> > > This one should compile on ppc, I even expect it to work for satasii on ppc. > AFAICS all programmer drivers except nic3com should work. > Compile with > make distclean > make NIC3COM=no > > > Known bugs: > > x86 is broken by this patch because the Makefile excludes the x86 > specific internal files. If you want to test this patch on x86 (to make > sure I didn't break everything), change > #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o > to > PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o > > boards_ok and boards_bad has no x86 guard yet and will end up in > flashrom -L output. >
Misha Manulis tested the patch and it didn't work. I found a typo which truncated all 16 bit and 32 bit LE write accesses to 8 bit. New version, should work fine with the x86/nic3com exceptions mentioned above. Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__ extern unsigned short segFS; @@ -122,3 +140,33 @@ return *(volatile uint32_t *) addr; } #endif + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Index: flashrom-ioport_x86_only/flash.h =================================================================== --- flashrom-ioport_x86_only/flash.h (Revision 984) +++ flashrom-ioport_x86_only/flash.h (Arbeitskopie) @@ -59,8 +59,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -402,6 +404,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -585,6 +593,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -592,6 +601,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-ioport_x86_only/spi25.c =================================================================== --- flashrom-ioport_x86_only/spi25.c (Revision 984) +++ flashrom-ioport_x86_only/spi25.c (Arbeitskopie) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -950,11 +952,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -24,13 +24,88 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#define ___constant_swab8(x) ((uint8_t)( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#else + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +237,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/spi.c =================================================================== --- flashrom-ioport_x86_only/spi.c (Revision 984) +++ flashrom-ioport_x86_only/spi.c (Arbeitskopie) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/Makefile =================================================================== --- flashrom-ioport_x86_only/Makefile (Revision 984) +++ flashrom-ioport_x86_only/Makefile (Arbeitskopie) @@ -121,7 +121,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -253,7 +254,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Index: flashrom-ioport_x86_only/satasii.c =================================================================== --- flashrom-ioport_x86_only/satasii.c (Revision 984) +++ flashrom-ioport_x86_only/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_le_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; } Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-ioport_x86_only/flashrom.c =================================================================== --- flashrom-ioport_x86_only/flashrom.c (Revision 984) +++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie) @@ -233,6 +233,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -250,6 +251,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { Index: flashrom-ioport_x86_only/internal.c =================================================================== --- flashrom-ioport_x86_only/internal.c (Revision 984) +++ flashrom-ioport_x86_only/internal.c (Arbeitskopie) @@ -99,9 +99,11 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -111,8 +113,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -149,10 +152,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) @@ -173,8 +179,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
