John,
I'll try making them coincide, maybe that'll work.
I have polygons on top & bottom (signal) layers, and split planes on
internal plane layers.
> -----Original Message-----
> From: John Haddy [mailto:[EMAIL PROTECTED]]
> Sent: Friday, May 18, 2001 3:03 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] DRC - overlapping spliit planes message
>
>
> I have split planes where the bounding vertices exactly coincide (on
> grid points) - and do not get this error.
>
> I just noticed that you mention polygon planes and split planes at
> the same time. I assume that this was just a verbal slip, and that you
> don't actually have drawn polygons on the power plane layer?
>
> John Haddy
>
> > -----Original Message-----
> > From: Dwight Harm [mailto:[EMAIL PROTECTED]]
> > Sent: Saturday, 19 May 2001 7:24 AM
> > To: 'Protel EDA Forum'
> > Subject: Re: [PEDA] DRC - overlapping spliit planes message
> >
> >
> > Steve,
> > Initially I had the boundary tracks just touching (10mil
> tracks on 10mil
> > centers). Now I've increased them to 12 mils, so the
> boundaries overlap,
> > which is what the help file indicates ("Using multiple Split
> > Planes in a PCB
> > design"), and still got the same result. I then pulled the
> top & bottom
> > polygon planes in a bit, so they're actually 5 mils smaller
> > (inside of) the
> > split planes, and still get the error.
> >
> > I also tried narrowing the split-plane boundaries down to 8mil,
> > resulting in
> > a tiny gap between the boundary tracks, and that still gets the
> > same error.
<snip>
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