Brad
You are correct. I just took a design routed with only one via size 25/12.
I changed the board design rule for vias to something radical like 15/5 and
ran the drcs... No errors are flagged. I guess this would be nice it
worked, I could use it.
Mike Reagan
EDSI
Frederick MD
----- Original Message -----
From: Brad Velander <[EMAIL PROTECTED]>
To: 'Protel EDA Forum' <[EMAIL PROTECTED]>
Sent: Friday, June 22, 2001 2:48 PM
Subject: Re: [PEDA] DRC for via sizing. Was: enhancements:
> HuH?
> Well I tried that report function on the vias that you mention
> Abd-ul Rahman, it certainly doesn't make any sense to me because I just
> tried it on a board that has an outline and components entered but no
> routing done. It does report my Routing Via Style for the size however, it
> reports a via count of 30 when there were absolutely no vias in the design
> yet. None in component footprints either. So again I state, huh?
>
> As for the Routing Via Style check in the DRC rules, the text
> comments in the upper right of the DRC window state "The maximum and
minimum
> via attributes are checked by the on-line and batch DRC." Obviously
another
> in the long list of Protel lies.
>
> Brad Velander,
> Lead PCB Designer,
> Norsat International Inc.,
> #300 - 4401 Still Creek Dr.,
> Burnaby, B.C., V5C 6G9.
> Tel. (604) 292-9089 direct
> Fax (604) 292-9010
> website www.norsat.com
>
>
> > -----Original Message-----
> > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, June 22, 2001 11:22 AM
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] enhancements:
> >
> > The Routing Via design rule seems to be intended for the
> > autorouter, as has
> > been noted by Mr. Velander, it is not a rule check.
> > There is, however, a manufacturing rule for annular ring.
> > This will detect
> > if any via has been modified such that it has insufficient
> > annular ring. If
> > the via has sufficient ring, I might suggest that "fixing" it
> > so that it is
> > the same as all the others might be intellectually satisfying but is
> > unlikely to improve the manufacturability of the board except
> > under certain
> > conditions:
> <SNIP>
> > There is a report option under
> > Report/BoardInformation/Report, Net Via
> > Size. It is unclear to me what it does. It provides what
> > appears to be a
> > report of via outer diameter, but the information as to
> > diameter seems to
> > come from the Routing Via rule rather than from the vias themselves.
> >
> <SNIP>
> >
> > [EMAIL PROTECTED]
> > Abdulrahman Lomax
> > P.O. Box 690
> > El Verano, CA 95433
>
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