On 07 Feb 2013, at 12:27, Graeme Geldenhuys wrote:Interesting, there is no mention of those limitations in the FPC 2.6.0 documentation. I looked in the RTL docs. It this is a concern, it is something that should be mentioned in the docs.
That has nothing to do with the programming language. This is about low level computer architecture. We don't claim that our documentation is a processor architecture manual. The interlocked* routines are documented as offering atomic accesses to memory locations, which is correct. The text doesn't suggest in any way that they also provide memory barriers, nor that they are sufficient to guard critical sections. That's what Enter/LeaveCriticalSection are for.
Do you know more specifically what platforms or CPU's are affected, so Michael could update the docs accordingly.
It doesn't belong in our manuals. Anyone who wants to manually create low level thread synchronisation primitives will have to know a lot more about cpu architecture and memory consistency models then we could ever describe in our documentation.
Does this limitation apply to all InterlockedXXX() functions?
Yes. Jonas _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
