On Thu, Feb 07, 2013 at 01:01:47PM +0100, Jonas Maebe wrote: > > On 07 Feb 2013, at 12:52, Jonas Maebe wrote: > > >It doesn't belong in our manuals. Anyone who wants to manually > >create low level thread synchronisation primitives will have to > >know a lot more about cpu architecture and memory consistency > >models then we could ever describe in our documentation. > > In case anyone is interested, some good documents on this topic are: > * > http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf > * http://www.kernel.org/doc/Documentation/memory-barriers.txt
Paul McKenney has written quite a lot about this, I find his "Memory Barriers: a Hardware View for Software Hackers" very useful. Henry _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
