On Tue, Mar 31, 2020 at 7:39 AM Sven Barth via fpc-devel <
fpc-devel@lists.freepascal.org> wrote:
> Am 30.03.2020 um 22:07 schrieb Christo Crause via fpc-devel:
>
> I've noticed GCC uses the SLLI + SRAI instructions to perform sign
> extension on ESP8266.
>
> Since different CPUs can support different subsets of the Xtensa
> instructions do you think a finalizecode type function can be used as a
> post code generation step to map unsupported instructions to alternative
> sequences?
>
>
> These are simply different CPU types (-CpXXX or selected by the controller
> type) which the code generator will handle accordingly. Just like it's done
> with ARM, AVR and all other platforms.
>
Attach please find a patch to rtl/embedded/MakeFile* to handle subarch
similar to avr and others.
Also attached a patch that checks whether the SEXT instruction is available
for the current subarchitecture, else it generates SLLI + SRAI combination.
I post the patches here for review since I'm not sure this is necessarily
the style to be followed when checking capabilities.
diff --git a/rtl/embedded/Makefile b/rtl/embedded/Makefile
index 117f0ea026..914e267df4 100644
--- a/rtl/embedded/Makefile
+++ b/rtl/embedded/Makefile
@@ -197,6 +197,12 @@ $(error When compiling for mipsel-embedded, a sub-architecture (e.g. SUBARCH=pic
endif
override FPCOPT+=-Cp$(SUBARCH)
endif
+ifeq ($(FULL_TARGET),xtensa-embedded)
+ifeq ($(SUBARCH),)
+$(error When compiling for xtensa-embedded, a sub-architecture (e.g. SUBARCH=lx106 or SUBARCH=lx6) must be defined)
+endif
+override FPCOPT+=-Cp$(SUBARCH)
+endif
ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)
TARGETSUFFIX=$(OS_TARGET)
SOURCESUFFIX=$(OS_SOURCE)
@@ -498,8 +504,10 @@ endif
endif
ifeq ($(ARCH),xtensa)
CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
+ifeq ($(SUBARCH),lx106)
CPU_UNITS=esp8266
CPU_UNITS_DEFINED=1
+endif
ifeq ($(CPU_UNITS_DEFINED),)
$(error No CPUs enabled for given SUBARCH, pass either a SUBARCH or set CPU_UNITS_DEFINED=1 if you know what you are doing)
endif
diff --git a/rtl/embedded/Makefile.fpc b/rtl/embedded/Makefile.fpc
index 0566231c3c..ff89dc336c 100644
--- a/rtl/embedded/Makefile.fpc
+++ b/rtl/embedded/Makefile.fpc
@@ -223,8 +223,10 @@ endif
ifeq ($(ARCH),xtensa)
CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
+ifeq ($(SUBARCH),lx106)
CPU_UNITS=esp8266
CPU_UNITS_DEFINED=1
+endif
ifeq ($(CPU_UNITS_DEFINED),)
$(error No CPUs enabled for given SUBARCH, pass either a SUBARCH or set CPU_UNITS_DEFINED=1 if you know what you are doing)
endif
diff --git a/compiler/xtensa/cgcpu.pas b/compiler/xtensa/cgcpu.pas
index a1fdbede87..f3e24b7365 100644
--- a/compiler/xtensa/cgcpu.pas
+++ b/compiler/xtensa/cgcpu.pas
@@ -167,14 +167,28 @@ implementation
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8));
OS_S8:
begin
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7));
+ if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7))
+ else if current_settings.cputype = cpu_lx106 then
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,24));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,24));
+ end
+ else
+ internalerror(2020033101);
if tosize=OS_16 then
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16));
end;
OS_16:
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16));
OS_S16:
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15));
+ if target_info.abi = abi_xtensa_windowed then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15))
+ else
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,16));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,16));
+ end;
else
conv_done:=false;
end;
@@ -258,7 +272,15 @@ implementation
list.concat(taicpu.op_reg_ref(op,reg,href));
if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7));
+ if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7))
+ else if current_settings.cputype = cpu_lx106 then
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg,reg,24));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg,reg,24));
+ end
+ else
+ internalerror(2020033101);
if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
a_load_reg_reg(list,fromsize,tosize,reg,reg);
end;
diff --git a/compiler/xtensa/cpuinfo.pas b/compiler/xtensa/cpuinfo.pas
index 0ee8adbcef..45ca53e249 100644
--- a/compiler/xtensa/cpuinfo.pas
+++ b/compiler/xtensa/cpuinfo.pas
@@ -133,7 +133,8 @@ Const
type
tcpuflags =
(
- CPUXTENSA_REGWINDOW
+ CPUXTENSA_REGWINDOW,
+ CPUXTENSA_HAS_SEXT
);
tfpuflags =
@@ -146,7 +147,7 @@ Const
(
{ cpu_none } [],
{ cpu_lx106 } [],
- { cpu_lx6 } [CPUXTENSA_REGWINDOW]
+ { cpu_lx6 } [CPUXTENSA_REGWINDOW, CPUXTENSA_HAS_SEXT]
);
fpu_capabilities : array[tfputype] of set of tfpuflags =
diff --git a/compiler/xtensa/xtensaatt.inc b/compiler/xtensa/xtensaatt.inc
index 90d556e946..340e62cb45 100644
--- a/compiler/xtensa/xtensaatt.inc
+++ b/compiler/xtensa/xtensaatt.inc
@@ -41,6 +41,7 @@
'sll',
'slli',
'sra',
+'srai',
'srl',
'srli',
'ssi',
diff --git a/compiler/xtensa/xtensaop.inc b/compiler/xtensa/xtensaop.inc
index 18ac2fd320..70b578e2d3 100644
--- a/compiler/xtensa/xtensaop.inc
+++ b/compiler/xtensa/xtensaop.inc
@@ -41,6 +41,7 @@ A_SEXT,
A_SLL,
A_SLLI,
A_SRA,
+A_SRAI,
A_SRL,
A_SRLI,
A_SSI,
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